clk_testout1 and clk_testout2 are used for camera handling, so add their ids.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 25fb42b1cf)
Change-Id: I8000e84264b032835cc3d11a6810264967f4248e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
we use SCLK_TESTCLKOUT1 and SCLK_TESTCLKOUT2 for camera, so add those ids.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit f22e4359cd)
Change-Id: Ibbdb8e9dabd8c955ef3745c0f49c20f4c763e870
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Export the dclk_vop_frac out, so we can set the dclk_vop as the
child of dclk_vop_frac, and then we can start to take use of
the fractional dividers.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 7b0f9e357a)
Change-Id: I08686f8ecbcfb5de7bc99aadd314f6e35ac22995
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Export the dclk_vop_frac out, so we can set the dclk_vop as the
child of dclk_vop_frac, and then we can start to take use of
the fractional dividers.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit e33075db73)
Change-Id: I3d47c6aecc338de45b48414f0d0327c17e6d2b15
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Currently the fractional divider clock time can't handle the
CLK_SET_RATE_PARENT flag. This is because, unlike normal dividers,
there is no clk_divider_bestdiv() function to try speeding up the parent
to see if it helps things.
Eventually someone could try to figure out how to make fractional
dividers able to use CLK_SET_RATE_PARENT, but until they do let's not
confuse the common clock framework (and anyone using it) by setting the
flag.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 29edeccb44)
Change-Id: Ic7fa067ed80767c937dd9c8506d2d1e86ee1c93a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We need to get the accurate 533.25MHz for the DP display.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 5c1c63f634)
Change-Id: Ib945c80451d52081683488fe410c5200622fb1c3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Usually, the 800MHz and 1GHz are supplied for CPLL and NPLL in the RK3399.
But dues to the carelessly copying from RK3036 when the RK3399 bringing up,
the refdiv == 6, it will increase the lock time, and it is not an optimal
configuration.
Let's fix them for the lock time and jitter are lower:
800 MHz:
- FVCO == 2.4 GHz, revdiv == 1.
1 GHz:
- FVCO == 3 GHz, revdiv == 1.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 1dfbec3905)
Change-Id: I725e8cb542afa7caf7cbb5ff6f747f65d48c5ced
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The PMU Cortex M0 on rk3399 is intended to be used for things like
DDRFreq transitions, suspend/resume, and other things that are the
purview of ARM Trusted Firmware and not the kernel. As such, the
kernel shouldn't be messing with the clocks. Add CLK_IGNORE_UNUSED to
these clocks.
Without this change, the following was observed on a Chromebook with a
rk3399 (using not-yet-upstream ARM Trusted Firmware code and
not-yet-upstream kernel code based on kernel-4.4):
1. We init the clock framework.
2. We start up "DDRFreq", which causes ATF to occasionally fire up the
M0 for transitions. Each time ATF fires up the M0 it will turn on
these clocks and each time it is done it will turn them off.
3. We finally get to the the part of the kernel that calls
clk_disable_unused() and we disables the clocks.
You can see the race above. Basically everything is fine as long as
ARM Trusted Firmware isn't starting up the M0 at exactly the same time
that the kernel is disabling unused clocks. ...but if the race
happens then we go boom.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 60aadea57e)
Change-Id: I2a78c74edc9bc5d5b4f26224ebdb34eb83afb022
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We need this rate to generate 100, 200, and 228.57MHz from the same
PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
an external display.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 4ee3fd4abe)
Change-Id: I118c877882d694b358697470225d8d94cb1271b5
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
There is a bit of headphone pop during power on, we
need to increase delay time (200us per loop step).
It looks fine that it may take 200us*128=25.6ms here.
Change-Id: Idbc5b235fd55c26cd71f4693cce98fccce60368f
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
rk3326 and other platform power management implementation
Change-Id: I34b9c773cfee1e684e833cdbcf687ac54cd8d88a
Signed-off-by: Zhang Yunlong <dalon.zhang@rock-chips.com>
The f_blocks of statfs include file system overhead，it is not normal
usage of Posix.
Change-Id: If481626b08c05290626938586e2dc721690f1a91
Signed-off-by: Cliff Chen <cliff.chen@rock-chips.com>
Add usic node for rk3399 USB 2.0 EHCI controller
with usic phy.
Change-Id: Ibb4179ff1479816daa3b8455b0229f8a7a05bbdf
Signed-off-by: William Wu <william.wu@rock-chips.com>
Some EHCI controllers use usic phy (e.g rk3399/rk3288),
in order to enable these controllers, we need to set
some additional EHCI vendor-specific registers.
Support this feature in device tree when using the ehci
platform driver by adding a new property for it.
Change-Id: I279ccfdb5866df49828825bfd41b39fcd58a2832
Signed-off-by: William Wu <william.wu@rock-chips.com>
During dwc3 resume, it shoudn't reset otg controller logic
if device is connecting with the otg port, because it will
cause device to be reenumerated. More seriously, it may
cause the otg_work to enter disconnect process and power
down usb3 controller power domain, at the same time, if
the xHCI driver is accessing the controller asynchronously,
it will cause system hang.
Change-Id: Id546277bd4082b7baeff830788643a800330ae8e
Signed-off-by: William Wu <william.wu@rock-chips.com>
When do core init, only reset the core for device mode.
Becasue in host mode, xHCI driver will reset the core
and its host block via usbcmd.hcrst. If we do core reset
in dwc3_core_init() for host mode, it will reset both
the dwc3 core registers and xHCI registers, and cause
device to be reenumerated when usb suspend/resume.
Change-Id: If723ce8a771975e9757d28cb2c114d6269581677
Signed-off-by: William Wu <william.wu@rock-chips.com>
By default, only using lrck_tx for PCM by hardware,
therefore, we need to use I2S_CKR_TRCM_TXONLY.
Change-Id: I6c4077e7e7e65b8a3a21416fd61d5900b3b72f42
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This patch using PCM rising late1 and slave mode for
Bluetooth HFP.
Change-Id: I4a0188134d7d0ef0690c6c7c9f94fc8ec50c1671
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
If there is only one lrck (tx or rx) by hardware, we need to
use 'rockchip,clk-trcm' specify which lrck can be used.
Change-Id: I3bf8d87a6bc8c45e183040012d87d8be21a4c133
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Python 3 requires parentheses in call to 'print', meanwhile
the 'line' could be bytes-like, let's decoding to str as utf-8.
This makes the gcc-wrapper.py compatible with both 2.7 and 3.
For example, a bytes-like string as below,
b'kernel/reboot.c:47:13: error: function declaration isn\xe2\x80\x99t a
prototype [-Werror=strict-prototypes]\n'
b' static void no_use()\n'
b' ^~~~~~\n'
After decoding, it looks like,
kernel/reboot.c:47:13: error: function declaration isn’t a prototype
[-Werror=strict-prototypes]
static void no_use()
^~~~~~
Change-Id: Icacdbe2ca7b7ab674ab90e54b79d3176e0061ac6
Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
The reserved root blocks is not enough for booting Android due to
the limit of 0.2% if the fs size too small. so we add a new mini-
mum limit is 128MB.
Change-Id: I5af3b182001d27e4d18b4090c5270bbb2ac6253b
Signed-off-by: Cliff Chen <cliff.chen@rock-chips.com>
Here should use the mapped grp as a reference, not idx.
Change-Id: Ia40dafc11f4f5f077f764f49985bb8d3ec800c28
Reported-by: Lin Jianhua <linjh@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
