This patch is to avoid fifo xrun in some timing case.
Change-Id: I511ebc4c443f1c3369fff1c4b4eb5faf145d5ae5
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Missing SNDRV_PCM_TRIGGER_SUSPEND/RESUME, usb-audio can not enter suspend
since pcm was always running.
Change-Id: I0f7be7345f2b5c1bd42dad4c6fc4647c8636eed8
Signed-off-by: zain wang <wzz@rock-chips.com>
we found mclk maybe not precise as required because of PLL,
but it still can be used and no side effect. for example, if we
require mclk 11289600, but get 11289598, it doesn't matter.
so using DIV_ROUND_CLOSEST to fix it.
Change-Id: If8453a7a08b319da81b07d572b02247bd7e7bd27
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
this patch add support for i2s bclk fs configuration, we can
configure bclk_fs by devicetree as required.
Change-Id: I7e034e0466793b5b9eab6566a43e90213f219bb0
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
The disvr usb audio sampling rate is through nanoc reported to
the kernel, so don't need the kernel again set the sampling rate.
Change-Id: I60409fc579952a196c4fe40f678e87d505a7508d
Signed-off-by: wjh <wjh@rock-chips.com>
Based on the TSADC Tshut mode to select pinctrl,
instead of setting pinctrl based on architecture
(Not depends on pinctrl setting by "init" or "default").
And it requires setting the tshut polarity before select pinctrl.
Change-Id: Iac9ca05073b0181ee13b0048d0c2a54204f82bca
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
to cope with Wide Temperature Range test, we maxamize
soc's sw/hw over temperature power off degree.
fow now, 115 degree Celsius is set to trigger sw powering off.
if sw function does not work and temperature is continuing to
grow up, and till 120 degree Celsius, hw powering off/reset
is triggered.
Change-Id: I751e9ea754f434bc20df39fdbdb40216a1582c39
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Define recovery key for uboot if uboot used kernel dtb
Change-Id: Iad91e1ba5109c82512d125981f0a26aa6cf1ddc2
Signed-off-by: Zain Wang <wzz@rock-chips.com>
If the device has a 'power-domains' property that the power framework
prefer to use dev_pm_ops for suspend&resume. The legacy suspend & resume
callback for nandc driver would not be used.
Anyway, it's better use dev_pm_ops whether 'power-domains' is existent.
Change-Id: I0e2822a44f3f0d458b778636cd84c5ae54505cf5
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
1.don't update vpc when record vpc equals 0 in gc progress
2.increase the number of read retry
3.avoid danger of abnormal power lost
4.change flash_read_page_raw return to error_ecc_bits
5.add nand buildin ecc support
6.skip ECC error page instead of marking as bad block
7.adjust the way of building tables to increase ftl init
Change-Id: I9ba24980c06d61a5a1d66019378075e0171a5887
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Rockchip socs often have some tiny number of muxes not controlled from
the core clock controller but through bits set in the pmugrf.
Use MUXPMUGRF() to cover this special clock-type.
Change-Id: Iac962a27a3c88ce188d03c416cb4b3b45a462c0a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add the clock tree definition for the new rk1808 SoC.
Change-Id: I86e502b27e0695c77e9937dfd7cffa14b5711954
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Update clock debugfs to support the below functionalities.
- Allow enable/disable a clock.
- Allow set_rate on a clock.
- Display available parent of a clock.
- Allow set_parent on a clock.
- Display the list of enabled_clocks along with prepare_count,
enable_count and rate.
Change-Id: Ib67b3a3409c9e7d8adb710bb524f54f543abf712
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This is because of the commit form upstream: commit 5ffa2aed38
("of: remove arch/$(SRCARCH)/boot/dts from include search path for CPP")
Change-Id: I6dc9eca4357f3425eb18fdc97b53e9923a421c33
Signed-off-by: Liang Chen <cl@rock-chips.com>
This modification is to solve the problem of hot plug failure when
SD card is inserted after boot, because det pin is initialized as GPIO
Change-Id: I1cd49faa92fa7502c23dd30c2c35fa712e5d0ea3
Signed-off-by: Chen Lei <lei.chen@rock-chips.com>
The property rockchip,phy_table is no longer used.
Change-Id: I11a84a0ffaf85d80c1a850abc666cea74f7f6e35
Signed-off-by: Zheng Yang <zhengyang@rock-chips.com>
