before:
text data bss dec hex filename
4919662 2289888 114376 7323926 6fc116 vmlinux
after:
text data bss dec hex filename
4817210 2235024 110208 7162442 6d4a4a vmlinux
Change-Id: I66ff62436bafa48242cec573901195220e84fbac
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
The current arm32 architecture does not yet support the
HAVE_LD_DEAD_CODE_DATA_ELIMINATION feature. arm32 is widely used in
embedded scenarios, and enabling this feature would be beneficial for
reducing the size of the kernel image.
In order to make this work, we keep the necessary tables by annotating
them with KEEP, also it requires further changes to linker script to KEEP
some tables and wildcard compiler generated sections into the right place.
When using ld.lld for linking, KEEP is not recognized within the OVERLAY
command, and Ard proposed a concise method to solve this problem.
It boots normally with defconfig, vexpress_defconfig and tinyconfig.
The size comparison of zImage is as follows:
defconfig vexpress_defconfig tinyconfig
5137712 5138024 424192 no dce
5032560 4997824 298384 dce
2.0% 2.7% 29.7% shrink
When using smaller config file, there is a significant reduction in the
size of the zImage.
We also tested this patch on a commercially available single-board
computer, and the comparison is as follows:
a15eb_config
2161384 no dce
2092240 dce
3.2% shrink
The zImage size has been reduced by approximately 3.2%, which is 70KB on
2.1M.
Change-Id: Id2c136f7c992c6699c6c576ada46bfb025378f78
Signed-off-by: Yuntao Liu <liuyuntao12@huawei.com>
Tested-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit ed0f941022515ff40473ea5335769a5dc2524a3f)
1. Fix the csc matrix. For YUV709L to YUV709L, YUV601L to
YUV601L, YUV2020L to YUV2020L, The csc matrix should be
identity matrix. For YUV601L to YUV709L, modeify the csc
matrix.
2. optimize the final calculation result. Use the new r2y
and y2r matrix for csc yuv2yuv and rgb2rgb case. A simple
round is used for csc yuv2yuv and rgb2rgb case for a more
precise result.
Change-Id: I51f1b597c2aa3edcb66bc359df709b9b61a97b52
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
This is the 6.1.84 stable release
* tag 'v6.1.84': (1865 commits)
Linux 6.1.84
tools/resolve_btfids: fix build with musl libc
USB: core: Fix deadlock in usb_deauthorize_interface()
x86/sev: Skip ROM range scans and validation for SEV-SNP guests
scsi: libsas: Fix disk not being scanned in after being removed
scsi: libsas: Add a helper sas_get_sas_addr_and_dev_type()
scsi: lpfc: Correct size for wqe for memset()
scsi: lpfc: Correct size for cmdwqe/rspwqe for memset()
tls: fix use-after-free on failed backlog decryption
x86/cpu: Enable STIBP on AMD if Automatic IBRS is enabled
scsi: qla2xxx: Delay I/O Abort on PCI error
scsi: qla2xxx: Change debug message during driver unload
scsi: qla2xxx: Fix double free of fcport
scsi: qla2xxx: Fix command flush on cable pull
scsi: qla2xxx: NVME|FCP prefer flag not being honored
scsi: qla2xxx: Update manufacturer detail
scsi: qla2xxx: Split FCE|EFT trace control
scsi: qla2xxx: Fix N2N stuck connection
scsi: qla2xxx: Prevent command send on chip reset
usb: typec: ucsi: Clear UCSI_CCI_RESET_COMPLETE before reset
...
Change-Id: If6edd552c88012d97f5eefc5e1d97a4f1683f171
Conflicts:
drivers/gpu/drm/bridge/sii902x.c
drivers/gpu/drm/rockchip/rockchip_lvds.c
drivers/media/i2c/imx335.c
drivers/usb/dwc3/gadget.c
drivers/usb/host/xhci-plat.c
sound/soc/rockchip/rockchip_i2s_tdm.c
The rk628's bt1120 encoder data type is yuv 4:2:2 packed format,
i.e., it supports four types of packing (YUYV, YVYU, UYVY, and
VYUY). The difference is that in the 16 lanel, there are 8
transmitting Y data, 8 transmitting UV data, and the UV data is
transmitted alternately. Adding these two properties can support
the packing method switching.
For example:
-- Assuming that these two properties are not configured, YUYV
format will be used to transfer data by default.
-- If you need to output YVYU format (i.e., the VU transfer order
is reversed), you need to configure the bt1120-uv-swap property.
-- If you need to output UYVY format (i.e., the Y and UV lane order
is reversed), you need to configure the bt1120-yc-swap property.
-- If you need to output VYUY format, both properties need to be
configured;
Type: Function
Redmine ID: N/A
Associated modifications: Ie1c54ac3fbc01d76d32eff8d2857f68339654b70
Test: N/A
Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: I25692e0713b68a8f9d7099086d00f927b9e26a02
// example:
&rk628 {
// case 1:
mode-hsync-pol = <1>;
mode-vsync-pol = <1>;
// case 2:
mode-sync-pol = <1>;
// case 3:
display-timings {
src-timing {
...
hsync-active = <1>;
vsync-active = <1>;
...
}
dst-timing {
...
}
}
}
Priority: case 3 > case 2 > case 1
-- case 1: the hsync and vsync polarities are configured by parsing
the values of the "mode-hsync-pol" and "mode-vsync-pol" properties
(if no property is configured, the corresponding polarity defaults to
positive polarity.
-- case 2: hsync and vsync polarity equal to "mode-sync-pol"
-- case 3: the "hsync-active" and "vsync-active" properties values in
the "display-timings"-"src-timings" node are prioritized to configure
the hsync and vsync polarity.
Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: I595651f0761ed77e5582e297977359ab7ddc1743
add and optimize information: bus_format, flag, clk, real_clk
For the rx side, clk is the actual frequency of the set clk_rx_read,
and real_clk is the actual clock frequency given by the detected
front end (which hdmirx sets into src_mode->clock).
For the tx side, clk is the set dst_mode->clock and real_clk is the
actual frequency of the set sclk_vop.
Type: Fix
Redmine ID: N/A
Associated modifications: N/A
Test:
console:/ # cat /d/rk628/5-0050/summary
input: HDMI
Display mode: 3840x2160p60 bus_format: YUV444
clk[594000] real_clk[594000] flag[5]
H: 3840 4016 4100 4400
V: 2160 2168 2178 2250
output: GVI
Display mode: 3840x2160p60 bus_format: RGB
clk[594000] real_clk[594000] flag[a]
H: 3840 4016 4100 4400
V: 2160 2168 2178 2250
csc:
csc[1], csc mode:BT709L_13BIT
system:
sw_hsync_pol:1, sw_vsync_pol:1
dsp_frame_h_start:0, dsp_frame_v_start:5
Signed-off-by: Zhibin Huang <zhibin.huang@rock-chips.com>
Change-Id: Ibb312aefeee68a6c882294e221b0ce9b3b3b6f98
Revert this commit as it wasn't reliably work as expected by massive test.
The problem is clear now that cxpl_debug_info from DWC core is missing
rdlh_link_up. So reading PCIE_PORT_DEBUG1 and check smlh_link_up isn't enough.
Quoted from DWC databook, section 8.2.3 AXI Bridge Initialization, Clocking and Reset:
"In RC Mode, your AXI application must not generate any MEM or I/O
requests, until the host software has enabled the Memory Space Enable
(MSE), and IO Space Enable (ISE) bits respectively. Your RC application
should not generate CFG requests until it has confirmed that the link is
up by sampling the smlh_link_up and rdlh_link_up outputs."
The problem was introduced by commit 1 and fixed by commit 2 but not to
the end. And finally commit 3 rename the register but not fix anything.
It was broken from the first time. Any dwc controller should be use the
buggy default method to check link up state. So revert this commit to use
our own link_up hook. The timing is drving smlh_link_up->L0->rdlh_link_up->
FC init(a fixed delay) from IC simulation. So the origin code is working. What
we were trying to fix is the link suddenly broke after link was already up.
However, it could happen anytime, even just after passing dw_pcie_link_up
check. So it's function drivers responsibility to check 0xffffffff return value
to be aware of the link broken state and do a proper retry or recovery.
[1]. commit dac29e6c54 ("PCI: designware: Add default link up check if
sub-driver doesn't override")
[2]. commit 01c076732e ("PCI: designware: Check LTSSM training bit
before deciding link is up")
[3]. commit 60ef4b072b ("PCI: dwc: imx6: Share PHY debug register
definitions")
This reverts commit a095b98601.
Change-Id: I2104e5fe00ac3be921f6dc1185ad3ce34e01d1bc
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
When s otp and ns otp are accessed simultaneously,
do not close the common clk to avoid reading failures.
Change-Id: Ic488e2053e99bf3413ba709ad17cf2fc1f95ad0b
Signed-off-by: Hisping Lin <hisping.lin@rock-chips.com>
SPI transmission exception is often caused by an abnormality in the
IRQ subsystem in the environment, so an attempt is made to switch
to the poll transmission scheme in order to expect the SPI module
to continue working.
Change-Id: I1fc0451efef501a5a462931515a25e48c4fd1765
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
This can balance performance and power consumption.
Change-Id: Ib59047632c57b6897098d16f43ba44e38e075c00
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Allow ADC-only headset mic detection when input key not needed
Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: Icd23a514861f535c488177a7554016c1d70ff118
Configure the "rockchip,tx-direction-b2a" property in DT can enable
B2A direction support for Rockchip mailbox V2 IP.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I005f2cebb3898ef895fd0be238711b65f3717690
Configure "rockchip,txdone-irq" property in DT indicates that the
controller can trigger the TX_DONE interrupt. This feature begin
support from RV1103B and RK3506 SoCs with Rockchip mailbox v2 IP.
If the mailbox client wants to use its own ACK to check TX_DONE,
the "rockchip,txdone-ack" property also gets reday for it in
this patch.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: Ie62d94c13f6d8081b08e8bf5c45b5f7de5204bbe
To avoid the caller signaling acquire_fence in some special cases (e.g.
interruptions), use the work queue to execute 'request_commit'.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Ibec2c8a7f5b5bd3e99d9109793561f28bfb7d4ac
When hdcp repeater's device count is 0, hdmi controller
will not update bstatus in hdcp1.4 ram. So bstatus should
be read via ddc directly.
Change-Id: I891f3824c0e77586c1180b118d38da4667e4a927
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
HFR1-17 requires that when the frl rate in edid
is protocol undefined, hdmitx must output the
maximum supported frl rate.
Change-Id: I61a0152d570e826207f51724578b0113e8818302
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
