pvi_waveform: update
1.support version 0x09, 0x16, 0x43 wbf file
2.fix lut table some err
3.remove no use code
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
Change-Id: I045dbc72064a00e15ac4eaff4b385ad853353b99
if pixels large than default which set in dtsi, use advanced-rates.
otherwise, use normal-rages.
Change-Id: I488c2815dbe1e3decd1d305a78bf523d944d1e96
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
1. move some gamma parameter from vop to vp;
2. add support atomic api for gamma lut;
Change-Id: Id54316fbbba4d07375fa51ca47790a01ea9c29f5
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
All modern devices support MSI or even MSI-X, but some very ancient devices
such as PCI devices may also like to only support PCI legacy INT. Although
it's very unlikely to happened but we at least need a method to make PCIe
work if anything wrong with GIC its support.
Change-Id: I917af7c8986977e3ae5944e9cc89a8e3409a8cd9
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
1/ enable CONFIG_PHY_ROCKCHIP_CSI2_DPHY
Use the rk3568 mipi dphy hw driver
2/ change HZ to 300
There is no need to keep HZ=1000 after commit 3be6453a90
("kthread: do not preempt current task if it is going to call schedule()").
3/ disable rockchip ebc dev driver by default
Signed-off-by: LongChang Ma <chad.ma@rock-chips.com>
Change-Id: Ie653a629791bbdbdbf0e8fdae77d2f802be946ac
We found a charger detection error on RK3566 Tablet.
1. Plug in a Type-C to Type-A cable and connect to PC USB Host
or USB charger, then the charger detection is normal.
2. Plug out the cable, then the charger disconnection detection
is normal.
3. Plug in a Type-C to Type-A receptacle and plug out again. Then
the charger is detected unexpectedly.
To fix this issue, reinitialize the cable state of USB charger to
EXTCON_NONE when USB charger is disconnected.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ic56e4ee865af129c222f4c90c3d6e753f4e785bd
Restore upstream commit 72b6bcb1a2 ("drm/rockchip: use DRM_FB_HELPER_DEFAULT_OPS for fb_ops")
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I523336e7d9374ed535c558e5ab49d9b8f89cfb8f
Crypto V2 regs should divided into two parts when rng is belonging
to crypto module.
Change-Id: Ib976851b845ff8cdccc607a677266bb61f54ae18
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
If rng reg set equle to crypto v2 reg, it should add 0x400 offset.
Change-Id: I591d20ea048090a3250cbc53f9dbb27a6c1b3660
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
API export&import is using feedback tfm, statesize should be equal to
feedback tfm's statesize, otherwise it will trigger WARN_ON in testmgr
module.
Change-Id: I450b74549dc962b93a0654d83869366868b78363
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
This reverts commit 2d36048f1c.
Which causes some confused behavior in suspend and resume.
Change-Id: Ibff257aea6bcecc9a012397d83a9d8a1ffd02132
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
method: when meets large resolution, higher clocks will be set.
if pixels less default_max_load, clocks use normal-rates setting.
otherwise, use advanced-rates instead.
Change-Id: I7e3c21903f02e3dbc7f84ea8084610ac76738c27
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
when cnt is more than codec_info size, then it may be overflow risk.
Change-Id: I7352118f425ccf263df0083c21ef0433f2322a43
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
If uboot logo is on, hdmi clock is need to record from crtc_state.
If not, hdmi may not be able to output audio.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I0a9c8bb5df0ab2bdb6d5d2754d92745aa7a2d0cf
For SGMII/QSGMII, RX data are not used, but mdio has input function,
therefor, also use the mdio to route for gmac mux.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: If238d4739863cac8673ba3c3b980a07034d57c11
Because phy1 is sata mode by default, and phy2 is pcie mode by default, when using qsgmii on phy1, it needs to be configured as pcie mode, because pcie mode is compatible with K28.1 and K28.5, while sata only has K28.5. If phy1 is in sata mode, qsgmii will not work, and both K codes need to be used at the same time. Based on this, we unified configuration into pcie mode.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Change-Id: I4a9e5a2cdcee448ec3457778bf4ee7135be70087
It should be prev_vp, vp is a fixed port in this function.
Change-Id: I7c5b1be4ecebbf6a3aee7766a0f8ecbcbf4951a1
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
bug:
[ 322.619045] PM: Syncing filesystems ...
[ 322.669563] mmc2: error -110 doing runtime resume
Disable DLL to reset emmc sample clock and the command conflict check
function after the controller has been reset or config clock to 375Khz.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ife306fdf1c8948e7ddef4d029b850735b43865e9
1.add vir_width/vir_height support
2.optimize the speed of get pvr lut table
Signed-off-by: Zorro Liu <lyx@rock-chips.com>
Change-Id: I32e1b66a4ee53a198e4c349107ae52e0a7d40145
the reg id will be used to find port id at uboot logo
Change-Id: If32ec28a3b1d30d20ded4229a767777bba0ea07a
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
when have task in running_list, it should be power off later.
Change-Id: I6df2d8ed11a05eba5753d78800c2175fc99ad0f1
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
