Adjust pvtm-voltage-sel table of cpu to calibrate cpufreq better.
Change-Id: I36f440eee378b3d6865d6beb148ee3a5677fcb22
Signed-off-by: Liang Chen <cl@rock-chips.com>
sually, RK EP is directly powered by RC, and the entire device
reset switch of EP is controlled by PERST#. If EP is powered
independently, EP will enter the initialization phase independently
of RC. In order to wait for the REFCLK provided by RC to stabilize,
the definition of reset-gpio has been added to identify PERST# gpio
signal translation.
Change-Id: I45f6d176a0a71615ccbbde11f419475ad8600dd3
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
In some cases, the discontinuous biphasic result may not be valid
after sleeping for specified time due to the interrupt preemption.
Therefore, it may be better to use the completion and set the actual
wait time to the 3/2 of the specified delay time.
Change-Id: Ib7ee5f7ceb53c195178e25d745985577fa8a6c4c
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
In some cases, the frequency result may not be valid after sleeping
for specified time due to the interrupt preemption. Therefore, it may
be better to use the completion and set the actual wait time to the
3/2 of the specified delay time.
Change-Id: I5b9879ff9eaaf41ace5534040e0e47ec9bca7cc0
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
If the &rockchip_pwm_biphasic_config.enable is set to false in
continuous biphasic counter mode, &rockchip_pwm_chip.biphasic_config
will be set to NULL after &rockchip_pwm_funcs.set_biphasic.
Without this patch, there may be the null pointer exception.
Fixes: 7a42db27aa ("pwm: rockchip: support for biphasic counter mode")
Change-Id: Ie6fb5e3b1c69ae055720716531ddebb64dbf30bf
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
After completing the initialization of serdes in uboot, enter the kernel
to perform initialization again
Change-Id: I689c30f55d9e259e5adaa95029f7523026cbed0a
Signed-off-by: Zitong Cai <zitong.cai@rock-chips.com>
After completing the initialization of serdes in uboot, enter the kernel
to perform initialization again
Change-Id: Ia603bd2b8892f1647d0c0fa37f38e1422f78a6b3
Signed-off-by: Zitong Cai <zitong.cai@rock-chips.com>
If the cluster sub wins are enabled, there will be POST_BUF_EMPTY
errors after entering the PSR mode, because cluster main wins are
disabled while the sub wins still are active. The patch can help
avoid these unexpected POST_BUF_EMPTY errors.
Change-Id: I3555e0c08c7c4eacf0ace472e3154693c03c6aa9
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Psr mode can help reduce power consumption when using the mcu panel,
which supports to refresh the image on its own while it remains
unchanged.
Change-Id: Ib9bd1bb472c996277eb374cc9ba1433ce3930d55
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
According to the following commits:
commit 9d0e3cac35 ("drm/atomic: Allow vblank-enabled + self-refresh "disable"")
commit 2bdba9d4a3 ("drm/rockchip: vop: Leave vblank enabled in self-refresh")
It is better to leave vblank enabled after entering the PSR mode, in
order to ensure that the vblank APIs (like DRM_IOCTL_WAIT_VBLANK) can
work in PSR mode. User space is not aware when the display system is
already in PSR mode, so this appears to be an API violation.
Without this patch, there may be a warning according to the following
check in drivers/gpu/drm/drm_atomic_helper.c:
static void
disable_outputs(struct drm_device *dev, struct drm_atomic_state *old_state)
{
......
ret = drm_crtc_vblank_get(crtc);
/*
* Self-refresh is not a true "disable"; ensure vblank remains
* enabled.
*/
if (new_crtc_state->self_refresh_active)
WARN_ONCE(ret != 0,
"driver disabled vblank in self-refresh\n");
else
WARN_ONCE(ret != -EINVAL,
"driver forgot to call drm_crtc_vblank_off()\n");
if (ret == 0)
drm_crtc_vblank_put(crtc);
......
}
Change-Id: I95ee15864c1dfa1045c41c7a9ed2985bb6107f2b
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
According to the following commits:
commit 9d0e3cac35 ("drm/atomic: Allow vblank-enabled + self-refresh "disable"")
commit 2bdba9d4a3 ("drm/rockchip: vop: Leave vblank enabled in self-refresh")
It is better to leave vblank enabled after entering the PSR mode, in
order to ensure that the vblank APIs (like DRM_IOCTL_WAIT_VBLANK) can
work in PSR mode. User space is not aware when the display system is
already in PSR mode, so this appears to be an API violation.
Without this patch, there may be a warning according to the following
check in drivers/gpu/drm/drm_atomic_helper.c:
static void
disable_outputs(struct drm_device *dev, struct drm_atomic_state *old_state)
{
......
ret = drm_crtc_vblank_get(crtc);
/*
* Self-refresh is not a true "disable"; ensure vblank remains
* enabled.
*/
if (new_crtc_state->self_refresh_active)
WARN_ONCE(ret != 0,
"driver disabled vblank in self-refresh\n");
else
WARN_ONCE(ret != -EINVAL,
"driver forgot to call drm_crtc_vblank_off()\n");
if (ret == 0)
drm_crtc_vblank_put(crtc);
......
}
Change-Id: Ide735636ab53fd6977de5034b8cfc4c8341220af
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The module NE160QAM-NX1 support eDP v1.4b with the following
features:
- Support resolutions 3840x2400p60 and 3840x2400p120
- 4 lanes eDP interface with 8.1Gbps link rates
- DPCD v1.4
- PSR(Panel self Refresh)
- DSC(Display Stream Compression)
Change-Id: I41361dc5500cd35234bfdc8436a50e3117c6fba2
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
