This adds a standalone driver to support PCIe hotplug functionality
merely based on a GPIO indicating the status of a downstream device
connectivity. It looks for "hotplug-gpios" property in the corresponding
device node to get the GPIO information.
It also provides a mechanism for platform drivers of the controllers
to register ops to perform any platform specific operations while
enabling/disabling the slots.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Link: https://patchwork.kernel.org/project/linux-pci/patch/20220930192747.21471-3-vidyas@nvidia.com/
Change-Id: Iafa798ee4d98f195f5d33d80120da0c569132548
before:
text data bss dec hex filename
4880931 2116804 107272 7105007 6c69ef vmlinux
after:
text data bss dec hex filename
4922448 2288868 118408 7329724 6fd7bc vmlinux
Change-Id: If066c764f6f17c35041f9f6a12afe255334b4f46
Signed-off-by: Lin Jianhua <linjh@rock-chips.com>
When switching sample rates, the clock settings are as follows:
- For 48K, MCLK = 256fs = 256 * 48K = 12288K
- For 16K, MCLK = 256fs = 256 * 16K = 4096K
- For 8K, MCLK = 256fs = 256 * 8K = 2048K
The `set_sysclk` function in the soc i2s_tdm controller does not
actually perform `clk_set_rate`; it merely passes the parameters.
The actual `clk_set_rate` is called during `i2s_tdm_hw_params`.
However, `rk817_hw_params` performs `restart_clk_apll` inside,
which sets the PLL parameters that do not match the MCLK,
resulting in silence. To resolve this, clk_set_rate for the MCLK
frequency should be called within the set_sysclk function.
Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: I3ad233542a5e8b16ae72f829e086a25f5be4a095
This patch will impact performance, so disable this feature by default.
This reverts commit 980a9f6834.
Change-Id: I8f7e2413049f92e87b4a915e9e597172ecb955ce
Signed-off-by: Liang Chen <cl@rock-chips.com>
According to SPI signal test results:
(1) When using SPI IOs under 3.3V power domain, need to increase
driver strength to level3.
(2) When using SPI IOs under 1.8V power domain, use default driver
strength(level2) is best.
Change-Id: I0404418256d4f9671393345bf44ffd4e285af584
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
1. Prevent data from crossing boundaries
2. Support GPIO_TYPE_V2_2 debounce config
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I57e295806a4f0f4002527daf77fe41f584a7e9e1
mclk pin has been addressed in i2s_8ch_mclk, and used by
codec, so, do not redefine it again in i2s_8ch_bus.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I74a3c3f817142ff4c313bbf9a39ced215f04feb6
1.mipi date rate need to set 1850Mbps
2.DSI RGB output need to set skip first frames
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
Change-Id: I0a339e339bd94dae66be682a4481a4b0cef8ff99
In some manufacturers, we have found that the i2c clk/data
pullup power is disabled when the system is shutdown or suspended,
As a result, the first i2c communication fails when probing
or resuming. Therefore, it is necessary to perform i2c
communication once by default when probing or resuming.
Change-Id: I0819d733ff3a6f9172c1d3bf7b8e5bf72bc52730
Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
For controller which is managed by PD (power-domain),
when PD off, the controller is reset to the default
status, and the FRAC-DIV is a fixed value(1/20).
Once the mclk is enabled, there are some high freq cycle
leak, to fix this issue, we use the pinctrl-idle to
block these cycles until the config has been come back
to the normal state.
Ref: commit 1f8e86a5ea ("ASoC: rockchip: pdm: Fix clk glitch on runtime PM")
Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: I8b1226896d8ca20293335a879452df732801f712
If "POST_CSC_DATA" property is used to transfer the csc
parameters, it need config the csc registers by the
parameters from "POST_CSC_DATA". Otherwise, It should
config the csc register by the parameters from the
connector bcsh property.
Change-Id: Ia126941d15d4403c6b690fcc6b7937f03ca71951
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
There is a ASYNC bridge between HCLK and SCLK domain.
On AUPLL case, we found RX data shift ahead 1-Bit on
TRCM-TX sometime (0.00x%), but it success on GPLL(50w+).
The root cause:
HCLK Domain: Config the XFER-3, pull up SIGNAL to HIGH.
SCLK Domain: SCLK_RX/TX samples the HIGH level to start.
Because HCLK Domain is async to SCLK Domain, So, there
is a risk that RX samels the HIGH Level, but RX not.
(at the edge XFER from LOW to HIGH)
Solution:
1, Gate the SCLK
2, Config the XFER-3
3, Ungate the SCLK
Thus, TX/RX Always samples the right Level at the same
time.
After this patch, Test passed over 50w+.
Test Script:
#!/bin/sh
count=0
killall aplay
sleep 1
while true
do
yes `echo -en "\x11\x11\x22\x22"` | tr -d '\n' | \
aplay -D hw:2,0 --period-size=1024 --buffer-size=4096 -r 192000 -c 2 -f s16_le &>/dev/null &
sleep 0.1
rxd=`io -4 0xfe470028 | awk '{print $2}'`
echo "[$count]: $rxd"
if [ "$rxd" != "22221111" ]; then
echo "FAIL: mismatch: $rxd, expected: 22221111"
break
fi
count=$((count + 1))
killall aplay
sleep .1
done
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I10258b92d2f62ab36b5ccc55e8bcc752f3af9d4f
Similar to the API clk_gate_endisable.
Can be replaced by API clk_gate_endisable directly
once the symbol exported been merged.
It's workaround for GKI.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I91a53734add53b3156afc2b03b25cdc207822331
Slave Resume Situation:
i2s-tdm acts as slave, and the external device, such as dsp
acts as master.
aplay -D hw:0,0 --period-size=1024 --buffer-size=4096 t.wav &
echo mem > /sys/power/state
the aplay was freeze and system go to sleep.
press the power-key to wakeup system, and now the aplay will
resume playback.
But, there is a case the external dev resume too slow to provide
clk to i2s-tdm, so, we need add a delay to make it resume well.
e.g.
&i2s {
rockchip,resume-deferred-ms = <1000>;
};
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: If9a82c8357cef23bd50305c585ee28794f45d347
