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Author SHA1 Message Date
Guochun Huang
c7a13590bd drm/bridge: dw-mipi-dsi: make lane byte clock cycles more accurate 
Change-Id: Ic510ef14161fdd1aa5441220520df50bb371ade4
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
 2021-09-03 17:48:03 +08:00
Guochun Huang
494a1a53f2 drm/rockchip: dsi: remove unused hs transition times table 
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I265dd0e8fdc0ca1e7b051e7364d7d3f833ddb596
 2021-09-03 17:48:03 +08:00
Guochun Huang
f195bf6963 drm/rockchip: dsi: fix reset sequence for master 
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I0c29df9c7dc03587a96e8206f6e82a08da0a797f
 2021-09-03 17:48:03 +08:00
Guochun Huang
31e9f77c4b drm/bridge: dw-mipi-dsi: remove the pclk which can be managed in runtime pm 
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Ib5287e452c0f40ab0bdaddf5a8f61f9d7abdb45a
 2021-09-03 17:48:03 +08:00
Guochun Huang
f5d16f932b drm/rockchip: dsi: dynamically manage the clock in runtime pm 
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: Idad08904c393f30b4bcc405edac09237696f5cf6
 2021-09-03 17:48:03 +08:00
Shawn Lin
d226c884fd mmc: sdhci-of-dwcmshc: Remove HS200 and HS400 at low speed for rockchip 
Rockchip platforms don't support HS200 or HS400 at low speed, so
we must limit it.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I40eb9f117fd83789b6ab7a16d44049e16786698b
 2021-09-03 17:45:56 +08:00
Cai YiWei
a2d74ca47b media: v4l: add API to clear unready device 
Change-Id: I497719e6e8f2ef25a9d6402c16733bf4318d06d7
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-09-03 11:26:07 +08:00
Shawn Lin
f463bdf4d8 arm64: dts: rockchip: rk3568: Set SDHCI core clk to 200MHz 
As we mask our SDHCI controller as SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
host->max_clk is derived from core clock in the first place. Then
f_max works together with it.

If we adjust loader's core clk setting, such as 50MHz, we will get
50MHz for host->max_clk, because .get_max_clock() reads core clk
when probing driver. That will lead f_max be set to 50MHz as well,
no matter if max-frequency is set higher than 50MHz.

We can simple solve this problem by assigning core clk as 200MHz
in the first place and then let max-frequency property takes over
it.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Idb2fdb8f68881d0286d977dc3718b74c30d3bc67
 2021-09-03 10:04:35 +08:00
Tao Huang
2c342bcc05 arm64: rockchip_gki.config: Enable CONFIG_PHY_ROCKCHIP_CSI2_DPHY 
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ia285c1c09f097a99ca6d76da5ae18094656659be
 2021-09-02 18:23:05 +08:00
Cai YiWei
d9b335b5d8 phy: rockchip: csi2-dphy: fix compile error 
Change-Id: I6afabfa78abe3202b308e8a4cfd547761bc2a6be
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-09-02 18:22:35 +08:00
Kever Yang
98e3dce8ad arm64: dts: rockchip: rk3588: Add support for multi-core 
RK3588 is an ARM DynamiQ architecture SoC, including 4 Cortex-A55 cores
and 4 Cortex-A76 cores.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: Id52349b39e28bc5a4fd3d0f17a712cd4c0797db8
 2021-09-02 18:02:18 +08:00
William Wu
bf6c596646 arm64: dts: rockchip: rk3588: add usb2 phy1 node 
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I9d8ce4b7e660b66a6d560502ccc895a2ec457173
 2021-09-02 16:36:32 +08:00
Tao Huang
621f6a5d90 arm64: dts: rockchip: Remove leading 0x from unit addresses in rk3588 
arch/arm64/boot/dts/rockchip/rk3588s.dtsi:921.32-933.4: Warning (unit_address_format): /iommu@0xfdc38700: unit name should not have leading "0x"
arch/arm64/boot/dts/rockchip/rk3588s.dtsi:935.32-947.4: Warning (unit_address_format): /iommu@0xfdc48700: unit name should not have leading "0x"

Fixes: e1e1eabccd ("arm64: dts: rockchip: rk3588s: Add mmu nodes for video codecs")
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: If259e78e4454266bccbbb51ee808f59c0e62ace7
 2021-09-02 16:34:20 +08:00
Frank Wang
95f6f44072 arm64: dts: rockchip: rk3588: add usbdp phy device node 
This adds USBDP combo PHY1 related nodes for RK3588 SoCs.

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I2afb41c8f57ab49c13ecee110a78c9b7f011e3fe
 2021-09-02 14:44:26 +08:00
Jon Lin
0e542bf348 arm64: dts: rockchip: rk3588s: add spi node 
Change-Id: I4e72251952f5aae5b9588c4c5cb00de4f70b7ae1
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2021-09-02 14:39:24 +08:00
William Wu
abdc763b77 arm64: dts: rockchip: rk3588s: add usb2 phy nodes 
The rk3588s has three independent USB 2.0 PHYs. And
each PHY has one port. The connection between the PHYs
and the controlles is as follows：

USB2 PHY0 to USB3 OTG0
USB2 PHY2 to USB2 HOST0
USB2 PHY3 to USB2 HOST1

Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I300dcf4fdf6e4688a7e1598e9e2f4bb17d48acbc
 2021-09-02 10:36:09 +08:00
William Wu
d8b7417bea usb: dwc3: core: allow pm runtime for rockchip platform 
Most of rockchip platforms support power domain for dwc3.
Allow the pm runtime to manage the power domain for dwc3
in the dwc3 runtime PM routine.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I49e3fa207db8aea0355a797b69c9c8a791d2eaa3
 2021-09-02 10:18:24 +08:00
William Wu
7e4881a49e usb: dwc3: core: use 2.0 clk for 3.0 if only support 2.0 mode 
If the dwc3 core is programmed to operate in usb 2.0 only
mode, and no usb 3.0 phy, then it needs to set the bit
DEV_FORCE_20_CLK_FOR_30_CLK of GUCTL1 to make the internal
2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe) clock.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Change-Id: I217a380815c21903c1090bd003c1d8ba2fadbe7c
 2021-09-02 10:18:23 +08:00
Jianqun Xu
7e6d99ae56 arm64: dts: rockchip: rk3399 add pd for iep_mmu 
Fixes: 239c747658 ("arm64: dts: rockchip: rk3399: add iep device node")

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Iec517750dd98af2d9814d97d7f3c2a9ff083f88a
 2021-09-02 09:56:40 +08:00
Jianqun Xu
9ee813b963 arm64: dts: rockchip: rk3399 fix rkvdec_mmu to vdec_mmu 
Fixes: a4e0ffd261 ("arm64: dts: rockchip: rk3399: add mpp support")

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ie325e610071fecb69128981b821023b862099459
 2021-09-02 09:49:20 +08:00
Yifeng Zhao
1a6396458b phy: rockchip: naneng-combphy: add support rk3588 
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Ice2a0219c3702dddeae91b4d0cb2dbbbcdb875fc
 2021-09-02 09:38:00 +08:00
Andy Yan
6a4797b6c4 drm/rockchip: vop2: Set correct possible_crtcs for writeback connector 
We only register used vp. So the registered crtcs may less than
the total vp on vop.

Fix warning:

[    0.495636][    T1] Bogus possible_crtcs: [ENCODER:345:Virtual-345]
possible_crtcs=0x7 (full crtc mask=0x3)
[    0.495681][    T1] WARNING: CPU: 0 PID: 1 at
drivers/gpu/drm/drm_mode_config.c:638
drm_mode_config_validate+0x1f0/0x2e8
[    0.495697][    T1] Modules linked in:
[    0.495717][    T1] CPU: 0 PID: 1 Comm: swapper/0 Not tainted 5.10.43
[    0.495730][    T1] Hardware name: Rockchip RK3568 EVB1 DDR4 V10
Board (DT)
[    0.495741][    T1] pstate: 60800009 (nZCv daif -PAN +UAO -TCO
BTYPE=--)
[    0.495751][    T1] pc : drm_mode_config_validate+0x1f0/0x2e8
[    0.495765][    T1] lr : drm_mode_config_validate+0x1f0/0x2e8
[    0.495777][    T1] sp : ffffffc01003b8c0
[    0.495786][    T1] x29: ffffffc01003b8d0 x28: 0000000000000000
[    0.495804][    T1] x27: ffffff8003b23580 x26: 0000000000000001
[    0.495823][    T1] x25: 000000000000000f x24: ffffff8003bc2750
[    0.495839][    T1] x23: ffffffc0114aa4b8 x22: ffffffc0114aa438
[    0.495851][    T1] x21: ffffff8003bb4368 x20: ffffff8003bb4368
[    0.495863][    T1] x19: ffffff8003bb4360 x18: ffffffffffffffff
[    0.495879][    T1] x17: 0000000000049705 x16: 00000000000d42dc
[    0.495896][    T1] x15: 0000000000000113 x14: ffffffc01003b550
[    0.495911][    T1] x13: 00000000ffffffea x12: ffffffc011bbb7b0
[    0.495928][    T1] x11: 0000000000000001 x10: 0000000000000001
[    0.495945][    T1] x9 : 0000000000000003 x8 : ffffffc011a5b808
[    0.495961][    T1] x7 : ffffffc011bbb808 x6 : c0000000ffffbfff
[    0.495977][    T1] x5 : 000000000005ffe8 x4 : 0000000000000000
[    0.495993][    T1] x3 : 00000000ffffffff x2 : ffffffc011a5b788
[    0.496008][    T1] x1 : 4effea469dba5e00 x0 : 0000000000000000
[    0.496026][    T1] Call trace:
[    0.496041][    T1]  drm_mode_config_validate+0x1f0/0x2e8
[    0.496057][    T1]  drm_dev_register+0x16c/0x1f0
[    0.496074][    T1]  rockchip_drm_bind+0x4f4/0x568
[    0.496087][    T1]  try_to_bring_up_master+0x15c/0x1c8
[    0.496096][    T1]  __component_add+0xb0/0x198
[    0.496104][    T1]  component_add+0x10/0x18
[    0.496120][    T1]  dw_mipi_dsi_rockchip_host_attach+0x28/0xd8
[    0.496136][    T1]  dw_mipi_dsi_host_attach+0xd0/0x120
[    0.496149][    T1]  mipi_dsi_attach+0x24/0x38
[    0.496165][    T1]  panel_simple_dsi_probe+0x94/0x1c8
[    0.496180][    T1]  mipi_dsi_drv_probe+0x1c/0x28
[    0.496195][    T1]  really_probe+0x20c/0x3e8
[    0.496209][    T1]  driver_probe_device+0x54/0xb8
[    0.496224][    T1]  device_driver_attach+0x6c/0x78
[    0.496238][    T1]  __driver_attach+0xb0/0xf0
[    0.496253][    T1]  bus_for_each_dev+0x68/0xc8
[    0.496267][    T1]  driver_attach+0x20/0x28
[    0.496281][    T1]  bus_add_driver+0x168/0x1f8
[    0.496296][    T1]  driver_register+0x60/0x110
[    0.496311][    T1]  mipi_dsi_driver_register_full+0x54/0x60
[    0.496328][    T1]  panel_simple_init+0x30/0x44
[    0.496339][    T1]  do_one_initcall+0x48/0x2d8
[    0.496349][    T1]  kernel_init_freeable+0x254/0x2c4
[    0.496365][    T1]  kernel_init+0x10/0x108
[    0.496380][    T1]  ret_from_fork+0x10/0x18

Fixes: d8d8a665cd ("drm/rockchip: vop2: Only register used vp to drm")
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I537b953d5597eeae70110e218892edca1e83a243
 2021-09-02 09:32:48 +08:00
William Wu
3e5172d097 arm64: dts: rockchip: rk3588: add usb3 otg1 controller node 
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I550e0fd3991179a4a62c1b762cc6b8358bf0f862
 2021-09-01 20:24:46 +08:00
Hu Kejun
a3344fee66 arm64: dts: rockchip: rk3399: add rkisp1 support 
Change-Id: Ie0eb7088d08f9c0cbd0443b6f9c635ade9b4cc8f
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
 2021-09-01 20:14:35 +08:00
Cai YiWei
206bd78433 media: rockchip: add rockchip isp format 
Change-Id: I0dd89290f23c412d4656583f554e220af66f9704
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-09-01 19:29:38 +08:00
Sandy Huang
e23f5f8435 arm64: dts: rockchip: rk3399: vop disable-device-link-resume 
Change-Id: I658764fb24f52a5ddc2cb42bfe4c023650fa0911
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2021-09-01 18:39:22 +08:00
Elaine Zhang
3bf21ceadc arm64: dts: rockchip: rk3399: fix pd_sd as sub domain of pd_perihp 
Change-Id: I62e53b85444f0f4bbb1d2e786a23ff1f91c89000
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
 2021-09-01 18:39:09 +08:00
Mark Yao
efdbbad34e arm64: dts: rockchip: rk3399: vop add reg-names and cabc lut 
Change-Id: Ia4b47301b58141b24e75e35544beb903325e0a19
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2021-09-01 18:37:18 +08:00
Mark Yao
8974a80274 arm64: dts: rockchip: rk3399: add dclk pll sources 
Change-Id: I0e29d67d5e3738b18a7407a049d216f8dcebb8e8
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2021-09-01 18:33:21 +08:00
Sandy Huang
e760deab18 arm64: dts: rockchip: rk3399: delete set assigned clk for vop aclk and hclk 
Change-Id: Iae51005277107b14755d0fd152fe4dbadeae33ce
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2021-09-01 18:33:00 +08:00
Ding Wei
a4e0ffd261 arm64: dts: rockchip: rk3399: add mpp support 
Change-Id: I56ff3ed1c49cf3524c9fe9284021c611c1a4b76c
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
 2021-09-01 18:04:09 +08:00
Shengfei Xu
661ac6db68 power: test_power: add testpower dts-config 
Change-Id: Ib2c78602f604d610a648397cbf08c56cdbd77eab
Signed-off-by: Shengfei Xu <xsf@rock-chips.com>
 2021-09-01 17:27:26 +08:00
Sugar Zhang
c0b196cd5b power: reset: reboot-mode: Register callback for kernel pre restart 
This patch register boot mode into kernel pre restart call chain
to support 'reset [cmd]'

e.g.

/# fiq
Welcome to fiq debugger mode
Enter ? to get command help
debug> help
FIQ Debugger commands:
 reset [<c>]   Hard reset with command <c>
debug>
debug> reset loader
DDR Version V1.04 20201030
DDR4, 328MHz
BW=32 Col=10 Bk=4 BG=2 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
...
boot mode: loader
...
RKUSB: LUN 0, dev 0, hwpart 0, sector 0x0, count 0x1d1f000

Change-Id: Ic1792bdd0262c77a09fd780c7ac3e6d912b09008
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2021-09-01 17:04:42 +08:00
Andy Yan
2c7919c02b power: reset: reboot-mode: treat unrecognized reboot mode as normal mode 
Some bootloader will check the reboot mode to take different action, so
we treat unrecognized reboot mode as normal mode to prevent the system
run into abnormal case.

Change-Id: I88063a5b41e4e645443229fa490b2b55db5ccf27
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2021-09-01 17:04:42 +08:00
Andy Yan
3c6335dce5 power: reset: reboot-mode: support parse boot mode 
Parse boot mode on system bootup, and export it to
userspace by sysfs: sys/kernel/boot_mode

Change-Id: I0158fc28f4dae51c798806006e49cead4ce2e923
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2021-09-01 17:04:42 +08:00
Tao Huang
3b939be7fb power: reset: reboot-mode: fix normal mode setup 
If cmd is empty in get_reboot_mode_magic, we should return normal magic.

Change-Id: I10931adc49e33f72ae73d9471159f82cc02ff0c0
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
 2021-09-01 17:04:42 +08:00
Joseph Chen
5187691184 mfd: rk808: remove duplicate content 
Change-Id: Ie2de3186579213c565c3b38a2c68955f2a7fd227
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
 2021-09-01 11:28:18 +08:00
Tao Huang
e0c0be6024 arm64: rockchip_gki.config: Enable CONFIG_ROCKCHIP_SUSPEND_MODE 
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I0298046864e1e3b88b5909ed30784bf0e2d496c2
 2021-08-31 18:12:16 +08:00
Tao Huang
5703bfaa81 arm64: rockchip_defconfig: update by savedefconfig 
reorder CONFIG_ROCKCHIP_SUSPEND_MODE only.

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I4d23e47e9123e73c2aaca498bb1ce6da86b91327
 2021-08-31 18:12:16 +08:00
Shengfei xu
31f3d7317e soc: rockchip: pm_config: set the suspend config to ATF 
Change-Id: I400aa252c24b814e3da7fa6703a4e03a1c90d572
Signed-off-by: Shengfei xu <xsf@rock-chips.com>
 2021-08-31 18:12:16 +08:00
shengfei Xu
d4174a3bdf soc: rockchip: pm_config: use new function to disable secondary CPUs 
System add the function suspend_disable_secondary_cpus to disable
secondary CPUs.

Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I770154cdb0c8f14b14e705d07604c44a4e3c1632
 2021-08-31 18:12:15 +08:00
Jianqun Xu
892d24b59b arm64: dts: rockchip: rk3588 add ioc node 
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I61235232fa98a2c4fe0d06de00a3a51132640a7e
 2021-08-31 18:11:16 +08:00
Simon Xue
eb86d472c3 arm64: dts: rockchip: rk3588s: add wdt node 
Change-Id: Iebf556fcba4a330bc819042d09c02a7da49601b3
Signed-off-by: Simon Xue <xxm@rock-chips.com>
 2021-08-31 18:08:20 +08:00
Simon Xue
523b04c03a arm64: dts: rockchip: rk3588s: add saradc node 
Change-Id: I0e8e972fc867cc8dd65b33244e68442b8d043b5d
Signed-off-by: Simon Xue <xxm@rock-chips.com>
 2021-08-31 18:04:14 +08:00
Cai YiWei
d600ace1e2 media: rockchip: isp/ispp to version v1.6.2 
Change-Id: I3959939530392f71313a3e30132d9746533f2d36
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-08-31 16:38:18 +08:00
Cai YiWei
bd01d85285 media: rockchip: ispp: first frame handle for multi dev 
Change-Id: Ie4bc4c8b8a7486fca6bd6b55ca395eb774997120
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-08-31 16:38:17 +08:00
Cai YiWei
10bf39031d media: rockchip: ispp: fix driver mode sync with ispserver 
Change-Id: Id3dad2f5c4e8a326f6c8541bdf75d8b8630b603d
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-08-31 16:38:16 +08:00
Cai YiWei
2e110a6dc4 media: rockchip: ispp: fix page fault due to scl exit early 
Change-Id: I8a7499a5d6e10707269525f7a0aa7a01b5aae7d6
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-08-31 16:38:15 +08:00
Cai YiWei
49be5cf622 media: rockchip: isp: add v-blank to procfs 
Change-Id: Ic62bf4b3fe26712ce4382025b1a234a55453c631
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
 2021-08-31 16:38:14 +08:00
Hu Kejun
bafe1aa446 media: rockchip: isp: fix set pdaf in dpcc error 
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
Change-Id: I1c1782091b0e011535b34b46c69a5cc805f3d103
 2021-08-31 16:38:14 +08:00