Commit Graph

1058798 Commits

Author SHA1 Message Date
Viresh Kumar
c83090bafb UPSTREAM: cpufreq: dt: Don't (ab)use dev_pm_opp_get_opp_table() to create OPP table
Initially, the helper dev_pm_opp_get_opp_table() was supposed to be used
only for the OPP core's internal use (it tries to find an existing OPP
table and if it doesn't find one, then it allocates the OPP table).

Sometime back, the cpufreq-dt driver started using it to make sure all
the relevant resources required by the OPP core are available earlier
during initialization process to properly propagate -EPROBE_DEFER.

It worked but it also abused the API to create an OPP table, which
should be created with the help of other helpers provided by the OPP
core.

The OPP core will be updated in a later commit to limit the scope of
dev_pm_opp_get_opp_table() to only finding an existing OPP table and not
create one. This commit updates the cpufreq-dt driver before that
happens.

Now the cpufreq-dt driver creates the OPP and cpufreq tables for all the
CPUs from driver's init callback itself.

Change-Id: Icd477646eb0eefeb01266e21064824d1b5ed6b46
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
(cherry picked from commit 873c9851eb)
2021-07-05 10:24:23 +08:00
Finley Xiao
7f0e1711ed soc: rockchip: opp_select: Export rockchip_nvmem_cell_read_u8/u16()
Change-Id: I1c231afce31da9f42cd92839540d8dcb675778ce
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2021-07-03 11:30:16 +08:00
Finley Xiao
01243dd90a soc: rockchip: opp_select: Remove non-essential conditions for getting pvtm
Change-Id: I929046fa5c36f9cbc01e30edaa68f9abdfccdfd6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2021-07-03 10:42:42 +08:00
Liang Chen
7628c13e4c soc: rockchip: opp_select: adjust opp-table by pvtm and mbist_vmin
1. support get pvtm from otp.
2. adjust opp-table by mbist_vmit which is get from otp.

Change-Id: Ie3703873880b65b2af03ae474065d541c7f9d605
Signed-off-by: Liang Chen <cl@rock-chips.com>
2021-07-03 10:42:20 +08:00
Wyon Bi
dd03e97b25 drm/panel: simple: Get panel-desc data from DT
Add the ability to parse panel-desc data from the devicetree if it's
not hard-coded data.

Change-Id: I474940282657c9aa03568b9f98916125784d9fcf
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2021-07-02 19:55:06 +08:00
Felix Zeng
5ce712564b arm64: dts: rockchip: rk3568: rknpu: Add rknpu cru reset
Signed-off-by: Felix Zeng <felix.zeng@rock-chips.com>
Change-Id: Ibc546e80e6f82f0e907505a1eec1e9d37231646a
2021-07-02 19:44:07 +08:00
Felix Zeng
aae79df0f6 arm64: dts: rockchip: rk3568: rknpu: Add new rknpu compatible with rk3568 target
Signed-off-by: Felix Zeng <felix.zeng@rock-chips.com>
Change-Id: I150aa58dc640cea47d30f89d7fefe500031cd074
2021-07-02 19:44:07 +08:00
Liang Chen
754a02572a arm64: dts: rockchip: rk356x: adjust opp-table for correlation chips
1. limit vmin of cpu/gpu/npu/logic by mbist_vmin.
2. raise vdd_logic when npu run at 1.0GHz or venc run at 400MHz.
3. disable npu@1.0GHz and venc@400MHz by default.
4. reduce vdd_logic for the chips with big leakage.
5. adjust low-temp-adjust-volt table.

Change-Id: If7ce6f010422d20e2dfd643a6894fa7304e6372f
Signed-off-by: Liang Chen <cl@rock-chips.com>
2021-07-02 19:42:24 +08:00
Ding Wei
1d4f962b53 arm64: dts: rockchip: rk3568: rkvenc: remove advanced-rates for safety
Change-Id: Ie1c4a45c084a6bc98359868db54c6a333489cd45
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
2021-07-02 19:42:09 +08:00
Liang Chen
25a9bdac78 arm64: dts: rockchip: rk3568: adjust opp-talbe when low-temp
Change-Id: I21a6394f9c4473ca6d98f46c2d2a9527e2eaabd2
Signed-off-by: Liang Chen <cl@rock-chips.com>
2021-07-02 19:38:44 +08:00
Finley Xiao
9a20200344 nvmem: rockchip-efuse: Fix later provider initialization
Possibly, provider driver initialization is later than
consumer driver. Use function subsys_initcall to initialize
NVMEM provider early to ensure NVMEM consumer doesn't need
to -EPROBE_DEFER.

Change-Id: I817aa44c3b34d2fdf44148e6b9649ceed76d8f1f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2021-07-02 19:34:29 +08:00
Finley Xiao
01c1a395d6 nvmem: rockchip-otp: Fix later provider initialization
Possibly, provider driver initialization is later than
consumer driver. Use function subsys_initcall to initialize
NVMEM provider early to ensure NVMEM consumer doesn't need
to -EPROBE_DEFER.

Change-Id: Ibaea188390a54d55eca2aa3585cace7bb8f37bb3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
2021-07-02 17:25:14 +08:00
Wyon Bi
620cc157a7 clk: rockchip: px30: Add CLK_SET_RATE_PARENT for clk_i2s0_tx_out_pre
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I18e86d31ece992af568fca12c9af2b04f327dd67
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-07-02 17:17:40 +08:00
Finley Xiao
969eda0685 clk: rockchip: px30: Add pll name for cpuclk
Change-Id: I4302071cfd29148fb33ba096f5f3bc2aeff1406e
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-07-02 17:17:40 +08:00
Wyon Bi
45e8903744 clk: rockchip: px30: Add CLK_SET_RATE_PARENT for clk_i2s1_out_pre
Change-Id: Ie01e78ecf49cbbc3101c7ff0fafff11d3428b271
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-07-02 17:17:40 +08:00
Sugar Zhang
2b1b3a5b70 clk: rockchip: px30: Export clk id for sclk_i2s0_tx/rx mux
Change-Id: I697d20fb0c69f9dcd76aaf2d18d666db2241360d
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-07-02 17:17:40 +08:00
Finley Xiao
03fb4f4b0f clk: rockchip: px30: Add support to set parent rate for vopl dclk
Change-Id: I208471f938b1795273c4f33ac35b82d667a2b312
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-07-02 17:17:40 +08:00
Finley Xiao
c6edde69b3 clk: rockchip: px30: Let npll only provide clock for vopl and gpu
As npll rate may be changed according to vopl dclk rate on px30.

Change-Id: I4abc042b49ee06436ba5d69dc8adfa9460da37f7
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-07-02 17:17:40 +08:00
Finley Xiao
fdd1e215f5 clk: rockchip: px30: Remove npll from gpu parent clock on px30
NPLL should provide clock for vopl dclk on px30, and its rate will be
changed according to vopl dclk rate, so GPU can't use npll as parent
on px30.

Change-Id: Ib2c8c57020405bcd14070dcd7bc71cbfe18230e3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2021-07-02 17:17:40 +08:00
Simon Xue
f2edd39115 iio: adc: rockchip_saradc: adjust SARADC_MAX_CHANNELS to 8
Change-Id: Ie2f4b8df770255b642257b30ace51f886c3b526b
Signed-off-by: Simon Xue <xxm@rock-chips.com>
2021-07-02 14:26:10 +08:00
Wyon Bi
fd54e4d301 phy/rockchip: Add driver for Rockchip Naneng eDP Transmitter PHY
DPTPHYT22ULP is designed for chips that perform eDP/DP data
communication while operating at low power consumption.
The main link is a multi-gigabit transmitter macro which
enable speed up to 4.0Gbps data transmitter with optimized
power and die size, also it can be easily fabricated and
implemented in a video system. The AUX channel is a halfduplex,
bidirectional channel consisting of one differential pair,
supporting the bit rate of about 1Mbps.

Macro consists of multi-main link transmitter channels,
AUX channel, one PLL and bias-gen unit. The main link
transmitter performs dedicated P2S, clock generator,
driver with preemphasis and self-test. Each of the channels
can be turned off individually.

Change-Id: Idf58991ff1bdd4557c4cfadf2dc047e95eca7668
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
2021-07-02 14:13:07 +08:00
Tao Huang
346f10249a arm64: rockchip_defconfig: Disable CONFIG_RUNTIME_TESTING_MENU
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ieaa1ed1175b4872e275e7577c91966ffff3d3b0d
2021-07-02 14:12:49 +08:00
Geert Uytterhoeven
e0e8b7d674 UPSTREAM: pinctrl: PINCTRL_ROCKCHIP should depend on ARCH_ROCKCHIP
The Rockchip GPIO and pin control modules are only present on Rockchip
SoCs.  Hence add a dependency on ARCH_ROCKCHIP, to prevent asking the
user about this driver when configuring a kernel without Rockchip
platform support.

Note that before, the PINCTRL_ROCKCHIP symbol was not visible, and
automatically selected when needed.  By making it tristate and
user-selectable, it became visible for everyone.

Change-Id: Ibaa8fddc0f667711bd6fc82fe1865cf65720c1c3
Fixes: be786ac5a6 ("pinctrl: rockchip: make driver be tristate module")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20210316134059.2377081-1-geert+renesas@glider.be
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit febb4ee23a)
2021-07-02 14:12:29 +08:00
Jianqun Xu
0dbff7b9e0 UPSTREAM: arm64: remove select PINCTRL_ROCKCHIP from ARCH_ROCKCHIP
Prepare to make pinctrl driver of rockchip to be module able, this patch
remove the select of PINCTRL_ROCKCHIP from ARCH_ROCKCHIP.

Change-Id: Ibc725c09c92e057b22a035b43b96c9e7c60d3f52
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Link: https://lore.kernel.org/r/20210305003907.1692515-2-jay.xu@rock-chips.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
(cherry picked from commit 25fda51ca3)
2021-07-02 14:12:29 +08:00
Yandong Lin
fb82ac8b70 arm64: dts: rockchip: rk3568: modify rkvdec compatible
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I0c0d927bd4c995f2be4570a5c2128acbf7f6cc63
2021-07-01 20:49:36 +08:00
Ding Wei
bbb0cd20ba arm64: dts: rockchip: rk3568: vepu && jpegd: Disable auto freqence set
reason: In rk356x, due to the hardware, vepu and jpegd should
disable auto freqence.

Change-Id: I2da5b5a7fc3b86180aef28b378a7b651e31a6b7a
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
2021-07-01 20:48:13 +08:00
Ding Wei
45a2f849bd arm64: dts: rockchip: rk3568: Set rcb-min-with=512 on rkvdec2
Change-Id: I0735307ea023517c731ed33387f5f074b0362841
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
2021-07-01 20:47:43 +08:00
Lin Jinhan
904ca96524 arm64: dts: rockchip: rk3568: add crypto node
Change-Id: Icb7a7e01ec83ebe01f32224108c102a1c7bf2fdd
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
2021-07-01 20:46:11 +08:00
Yifeng Zhao
8a38d9f53b arm64: dts: rockchip: change naneng combphy ref clock to 100mhz for rk3568
When using 24MHz reference clock, some devices can't identify
the SATA PM chip, And the signal quality is not as good as 100MHz.
so change the reference clock to 100MHz.

Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: If7d951a0b77d503f9faf1c1f88c78a9e07471e47
2021-07-01 20:45:44 +08:00
Cai YiWei
3d0af15013 arm64: dts: rockchip: rk3568: isp iommu v2
Fixes: 28f15a4887 ("arm64: dts: rockchip: rk3568: add isp node")
Change-Id: I1959b21216e539ad4dc482262496c99ccbc3db30
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
2021-07-01 20:45:22 +08:00
Shawn Lin
dc141f807f mmc: core: Add a timeout value for flushing cache
In order to silent the warning below:

mmc0: unspecified timeout for CMD6 - use generic

Fixes: 4734c45258 ("mmc: core: don't check card status when flushing cache")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I561fd8592c646a61d22b04e27a0fc0a6c9b01f4e
2021-07-01 16:21:35 +08:00
Jon Lin
3c6a5390ca arm64: dts: rockchip: rk3568: Set spi node to fall back point
Both rk3568' spi is compatible with rk3036's spi design.

Change-Id: I952beb57c151e77165db781bc17ec782b6bc62a4
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2021-07-01 16:01:58 +08:00
Sandy Huang
8c8f462197 drm/rockchip: driver: fix sub_dev pointer error
the sub_dev will be update by list_for_each_entry() and return !NULL
error pointer when no found subdev;

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I8d7db3b66c6c57b986a42cac9ed6eca53b72611e
2021-07-01 14:29:01 +08:00
Tao Huang
89d6a276b6 arm64: rockchip_defconfig: merge s/android-5.10 android base config
https://android.googlesource.com/kernel/configs
commit 46f8bc810fbe ("Finalize min LTS version for S.")

android-base.config and android-base-conditional.xml:

-# CONFIG_RD_LZ4 is not set
+CONFIG_USERFAULTFD=y
+CONFIG_SHADOW_CALL_STACK=y
+CONFIG_XFRM_MIGRATE=y
+CONFIG_SONY_FF=y
+CONFIG_ANDROID_BINDERFS=y
+CONFIG_CRYPTO_CHACHA20POLY1305=y
+CONFIG_CRYPTO_XCBC=y
+CONFIG_KFENCE=y

from gki_defconfig:
+CONFIG_KFENCE_SAMPLE_INTERVAL=500
+CONFIG_KFENCE_NUM_OBJECTS=63

RD_LZ4:
Support future decompression of LZ4-compressed ramdisk images.

USERFAULTFD:
Patches for SELinux support and kernel page-fault restriction in
userfaultfd have been backported.
So from security perspective it should be safe to enable it in Android.

XFRM_MIGRATE:
To be able to update addresses of an IPsec SA, as required by
supporting MOBIKE

CHACHA20POLY1305 and XCBC:
To be able to use ChaCha20Poly1305 and AES-XCBC in IPsec

CONFIG_KFENCE_NUM_OBJECTS controls the constant memory overhead that
KFENCE introduces for its memory pool. By default it is 255 objects
(2Mb extra memory), but since concerns have been raised that low-memory
devices may not afford that, we are lowering the number of objects
to 63 (512Kb extra memory).

So far we haven't seen Android devices allocate more than 50 KFENCE
objects. Should the kernel exhaust the pool, KFENCE will stop allocating
new objects and fall back to SLAB/SLUB until one of the objects is
freed.

An immediate consequence of reducing the pool size is that a freed
KFENCE object will be reused 4x times faster, effectively reducing the
probability of detecting a use-after-free. Since KFENCE is a best-effort
error detection tool, not a use-after-free mitigation mechanism, we
believe this should not be problematic.

enable KFENCE by setting the sample interval to 500ms
It is still possible to disable KFENCE at boot time using
kfence.sample_interval=0.

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I061f3caf0d09adfd4e0c322853aeff5af8ba63a5
2021-07-01 10:25:15 +08:00
Tao Huang
6cd279bd4e arm64: rockchip_defconfig: Remove legacy IO schedulers
According to commit f382fb0bce ("block: remove legacy IO schedulers").

-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_CFQ_GROUP_IOSCHED=y

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ia20d8fe921b4ff0e4b8507ef665cae865704f717
2021-06-30 20:15:22 +08:00
Jianqun Xu
57c92c0734 scripts: dtc: delete empty node after omit_unused_nodes
A node is empty node if its proplist/label/child both null or both
set as deleted.

Change-Id: Ia934c58df3305dc9531cc912322eb2728f7af689
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2021-06-30 18:56:26 +08:00
Jianqun Xu
6e488e859f PM / devfreq: add to show current load of device
Calculate current load with busytime / totaltime from status,
also show the current frequency.

Change-Id: Ic310035db9c5478aa3d0b1e526b47c451fe09d23
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2021-06-30 18:26:24 +08:00
Jianqun Xu
d85e70122d PM / devfreq: rockchip-dfi: disable irqs during accessing ddr monitor
Change-Id: Ie4817a77fcb1283f37f41ab097f02ed7dc9cd18c
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2021-06-30 18:22:28 +08:00
Sandy Huang
030d591fd8 drm/rockchip: driver: add support more property
Change-Id: If2cbc617d9346713efaf7dc4dd5c393e8605f91d
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
2021-06-29 20:33:40 +08:00
Tao Huang
607584914c arm64: rockchip_defconfig: Disable N1/A77/CAVIUM/FUJITSU ERRATUM
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I8dfdf8576e90528aad0b4e0cc860b32836de2ef3
2021-06-29 20:14:35 +08:00
Tao Huang
4fad62b702 arm64: rockchip_defconfig: Enable CONFIG_THERMAL_GOV_POWER_ALLOCATOR
default y on 4.19.

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ie65631ab968fe54504a33a08f004474e5979f2ad
2021-06-29 20:14:35 +08:00
Tao Huang
127d788a7f arm64: rockchip_defconfig: Disable CONFIG_TEE_SUPPORT
security/optee_linuxdriver is deprecated.

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I6b731d789c31d213dc116d431fb29a381fb5287a
2021-06-29 20:14:35 +08:00
Tao Huang
20c0820771 arm64: rockchip_defconfig: update by savedefconfig
Remove unsupported configs:
-CONFIG_SCHED_TUNE=y
-CONFIG_CRYPTO_CRC32_ARM64_CE=y
-CONFIG_DM_VERITY_AVB=y
-CONFIG_DM_ANDROID_VERITY_AT_MOST_ONCE_DEFAULT_ENABLED=y
-CONFIG_ANDROID_VERSION=0x08000000
-CONFIG_EXT4_ENCRYPTION=y
-CONFIG_F2FS_FS_ENCRYPTION=y
-CONFIG_SECURITY_PERF_EVENTS_RESTRICT=y

Default n:
-# CONFIG_COMMON_CLK_XGENE is not set

Default y:
-CONFIG_IIO_BUFFER=y
-CONFIG_IIO_KFIFO_BUF=y
-CONFIG_IIO_TRIGGER=y

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I52c42ee08f425c152d51f26901c1eb6a374ebbec
2021-06-29 20:14:35 +08:00
Andy Yan
7aaf92a036 drm/rockchip: lvds: sync from 4.19
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I167963980a3978e77ab6f2fdeca29ba2bd28db1b
2021-06-29 19:30:25 +08:00
Sandy Huang
9cbe0679b6 drm/rockchip: add rockchip_drm_sub_dev_list to record connector
use rockchip_drm_sub_dev_list to manage rockchip drm sub dev and record
connector, offer new method to find connector through the sub_dev_list.

Change-Id: If9508cf9ff51f6f9e1d13c42c60491f4aec4b9c1
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
2021-06-29 19:22:52 +08:00
Andy Yan
e955b10e28 drm/rockchip: Add rockchip_drm_of_find_possible_crtcs() function
When get possible_crtcs for a encoder, skip the inactived endpoint, this
make userspace more clear about which crtc this connector should attached
to.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I4221491307193209482fd9477a492ebba613c7ad
2021-06-29 19:18:15 +08:00
Andy Yan
ee2b4a4f87 arm64: dts: rockchip: rk3568: Add disable-device-link-resume for vop iommu
We don't want to call rk_iommu_enable when iommu driver resume.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I5bd1ac97522af42b0e6178c28ed714c5f5d5206b
2021-06-29 14:57:37 +08:00
Jianqun Xu
81ad67699f ARM: dts: rockchip: pinconf.dtsi add output level with pull up/down
Change-Id: Id40ca9a6efbbfa05df6bc4ebe36a07874b9a837d
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2021-06-29 14:52:26 +08:00
Jianqun Xu
7fbdf804c1 arm64: dts: rockchip: pinconf.dtsi add output level with pull up/down
Change-Id: I3ce795514365e3f7f2302dfbc1deb73884b645be
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2021-06-29 14:51:39 +08:00
Jianqun Xu
853ce8706f soc: rockchip: io-domain: support rk3568
Change-Id: I097898c8f19dbd5f7caa1798bebd2506876cffc3
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2021-06-29 14:50:08 +08:00