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Author SHA1 Message Date
Caesar Wang
d95072a003 arm64: dts: rockchip: adapter boards configuration for rk3566 
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: I13acc6238bf7512a8327c23dc1a0991d23d48ddf
 2020-11-12 15:34:10 +08:00
David Wu
8f4b73ffda arm64: dts: rockchip: rk3568-evb: Change the delayline for gmac0 and gmac1 
Change-Id: Ia5ee198234562045c028af8d3c3b6f3210efe4ac
Signed-off-by: David Wu <david.wu@rock-chips.com>
 2020-11-12 15:19:21 +08:00
Algea Cao
a46506e8d1 drm: rockchip: dw-hdmi: Add ddc_en_reg description 
Fixes: cdbb863092 ("drm: rockchip: dw-hdmi: Enable 3568 hdmi ddc")
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I424a7235b775aed9510831e6df1a3d9a012d6923
 2020-11-12 15:12:33 +08:00
Algea Cao
2665bc4a84 drm: rockchip: dw-hdmi: Introduce HCLK_VOP for RK3566/RK3568 
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ifcc15490b135692d955500114b59cbf8c326cacd
 2020-11-12 15:03:14 +08:00
Algea Cao
aa501b29ee arm64: dts: rockchip: rk3568: Add HCLK_VOP for hdmi 
If hdmi doesn't enable HCLK_VOP, clock reference
count will be abnormal and may cause system stuck.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ibe01d029d1ae69f9f32d4cd0eb149bf72a662381
 2020-11-12 15:02:34 +08:00
Shunqing Chen
3c97807997 arm64: dts: rockchip: rk3568-evb: fix issue of hdmi no sound 
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Change-Id: Ic3a3366c8336e86ef62cd8af270b4c938832c9ec
 2020-11-12 14:27:57 +08:00
Alex Zhao
a68d8fa144 arm64: dts: rockchip: rk3568-evb1-ddr4-v10 :add wifi/bt for evb1 
Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Change-Id: I9cc3bfe1258ba972474e3e60197d0bdb8878e06d
 2020-11-12 14:19:44 +08:00
Andy Yan
489331887b drm/rockchip: vop2: Check the max output width for video port 
Mark the display mode which request a unsupported output width
as MODE_BAD_HVALUE.

Change-Id: I5d4dbefb8cdd97d54512f6a8e4c9de74d849ea89
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2020-11-12 14:06:06 +08:00
Andy Yan
925153dae7 drm/rockchip: vop2: Convert 10 bits output mode to 8 bits for vp max bpc is 8 
Not all the video ports support 10 bit output, so
we need do a convert here.

Change-Id: I6dbb0c23e9cc1ceaf295e2771606705dacd37994
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2020-11-12 14:06:06 +08:00
Andy Yan
48c83387b1 drm/rockchip: vop2: Add unique share id for Cluster window 
This make Android hwc happy.

Change-Id: I1b83d512dcd553b2f98e52b808628f71657a1516
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2020-11-12 14:06:06 +08:00
Andy Yan
75a451f7d9 drm: debugfs: No write dump buffer when crtc is not active 
No framebuffer to dump when crtc is not active.

Change-Id: If05c629644653121f3fd97229eb845ffa30bf941
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2020-11-12 14:06:06 +08:00
Andy Yan
02deab7718 drm/rockchip: vop2: Add multi area scl support 
Add multi area scaler register.

Change-Id: I1f47f77d444f5cd83a61a31390b4ed5d8558caa6
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2020-11-12 14:06:06 +08:00
Sugar Zhang
b52bf64a33 arm64: dts: rockchip: rk3566-evb1-ddr4-v10: Add audiopwmout differential 
Change-Id: I5e3631b9d39cb6c213e6d6994b05a66b1ef4bc94
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2020-11-12 12:17:43 +08:00
Sugar Zhang
65f13f2ee6 arm64: dts: rockchip: rk3568-evb: Add audiopwmout differential 
Change-Id: Ifca7a65357137d44326cdf0f5dcec0d35b42b3a1
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2020-11-12 12:17:20 +08:00
Sugar Zhang
279398feba arm64: dts: rockchip: rk3568-pinctrl: Fix iomux for audiopwm 
Change-Id: If6e4bdc04f669dbe06149de24cf1030f66f409d9
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2020-11-12 12:16:52 +08:00
Sugar Zhang
2b2357f465 arm64: dts: rockchip: rk3568: Add CLK_ACDCDIG_I2C for dig_codec 
Change-Id: I74b873c03773a60451e6a829dd27fa6e4774a34e
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2020-11-12 12:16:19 +08:00
Sugar Zhang
6cf335aa30 arm64: configs: rockchip: Enable digital codec interface 
Digital codec interface is used with external codec analog part
with pdm link(e.g.: rk812) or audiopwm out differential.

Change-Id: Ic649cf1861cdcd493d52176a627ba7bbdf3338ae
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2020-11-12 12:04:35 +08:00
Sugar Zhang
ee5f3c03ef ASoC: codecs: rk_codec_digital: Restore register when pm runtime_suspend/resume 
Change-Id: I0730f50faa3fea1823570dd7390ac760efbfe99f
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2020-11-12 12:04:10 +08:00
Sugar Zhang
271b62097e ASoC: codecs: rk_codec_digital: Add CLK_I2C handling 
Change-Id: Ia4320952d55840d95ac22ae230d3e264f86e62d0
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2020-11-12 12:04:10 +08:00
Alex Zhao
89654b82e2 arm64: rockchip_defconfig: add uart number to 10 
Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Change-Id: Ifecbebaf84c74ba4b7566192f661c94c1af1d30d
 2020-11-12 11:43:01 +08:00
Sandy Huang
05d15d5e4a arm64: dts: rockchip: rk356x-evb: move dsi config position 
Change-Id: I01f64a949638c66972fbe57895a5488e0dbc2d59
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
 2020-11-12 11:26:01 +08:00
Sugar Zhang
c9ce134b3d ASoC: codecs: rk_codec_digital: Removed unused clk handling 
This patch remove unused clk handling, instead, clk handled by
pm runtime.

Change-Id: I1f183efebdb909440bf9c31fb63d7d22d21953c0
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2020-11-12 11:24:38 +08:00
Sugar Zhang
26c997483d ASoC: codecs: rk_codec_digital: Add support for pwm outout mode 
Change-Id: Ia359c32fdddc1ed5b63b52b8c676fada1391da71
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2020-11-12 11:24:38 +08:00
Ding Wei
45805626ea arm64: rockchip_defconfig: enable mpp relative codec 
CONFIG_MPP_ROCKCHIP_RKVDEC2: rkv-decoder-v2
CONFIG_MPP_ROCKCHIP_RKVENC:  rkv-encoder-v1
CONFIG_MPP_ROCKCHIP_JPGDEC:  rkv-jpeg-decoder-v1

Change-Id: Ia98a2908caaaff24f5df4ec507590b276fc15ca5
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
 2020-11-12 11:17:45 +08:00
Weiguo Hu
103827124a net: wireless: rockchip_wlan: realtek wifi: avoid illegal argument when called by ioctl SIOCDEVPRIVATE 
Illegal argument will cause following kernel panic.

Call trace:
  PHY_SetRFReg_8723B
  rtw_hal_write_rfreg
  rtw_wx_write_rf
  _rtw_ioctl_wext_private
  rtw_ioctl
  dev_ifsioc
  dev_ioctl

References: CNVD-C-2020-259508
Signed-off-by: Weiguo Hu <hwg@rock-chips.com>
Change-Id: Ia493d8276c1dd414c184a9b3eddb5d252bd85b98
 2020-11-12 11:12:21 +08:00
Tao Huang
21f2c43755 arm64: dts: rockchip: rk3568-evb1-ddr4-v10: Sort labels alphabetically 
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I5266ca57f246643abac7eb99ad24c091eb8c88ab
 2020-11-12 10:53:16 +08:00
Elaine Zhang
81e4b17554 clk: rockchip: rk3568: mark clk_optc_arb as critical clock 
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I63e9b332adeacbebd12df758b0f56b0753598f4c
 2020-11-12 10:19:44 +08:00
Finley Xiao
0d652a751c dt-bindings: rockchip-thermal: Support the RK3568 SoC compatible 
Add a new compatible for thermal founding on RK3568 SoC.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I5ec192a380ffb331120fa0fed20df83d5d83e8d9
 2020-11-12 10:14:08 +08:00
Andy Yan
a83c953054 drm/rockchip: vop2: Show plane dump information better 
Change-Id: Id86d8805034e64be9c5008321941d0947b93c506
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2020-11-12 09:13:42 +08:00
Simon Xue
bdbd6ca828 iommu/rockchip: fix v2 domain free 
Change-Id: I73108579bada8389d36a8d4a60d9a12e81ed718a
Signed-off-by: Simon Xue <xxm@rock-chips.com>
 2020-11-11 22:08:55 +08:00
William Wu
fefd47dc10 usb: dwc3: core: only set DEV_FORCE_20_CLK_FOR_30_CLK for high speed 
Fixes: 5f0c2578ed ("usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode")
Change-Id: I7082d996979c4f52f898403e25853644e956cf48
Signed-off-by: William Wu <william.wu@rock-chips.com>
 2020-11-11 22:06:46 +08:00
William Wu
096abe6464 phy: rockchip: naneng-combphy: select pipe to controller for rk3568 
RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers
share one pipe interface for each combo phy, here is the diagram of
the complex connection. This patch select the pipe to the corresponding
controller when set phy mode.

+----------------+
|                |     +------+
| USB3 OTG CTRL0 |---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY0 |
+----------------+     |      |     |            |
|                |     |      |     +------------+
|   SATA CTRL0   |---->|      |
|                |     +------+
+----------------+

+----------------+
|                |     +------+
| USB3 HOST CTRL1|---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY1 |
+----------------+     |      |     |            |
|                |---->|      |     +------------+
|   SATA CTRL1   |  -->|      |
|                |  |  +------+
+----------------+  |
                    |
+----------------+  |
|                |  |  +------+
|  QSGMII CTRL   |---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY2 |
+----------------+     |      |     |            |
|                |---->|      |     +------------+
|   SATA CTRL2   |  -->|      |
|                |  |  +------+
+----------------+  |
                    |
+----------------+  |
|                |  |
|  PCIe2 1-Lane  |---
|                |
+----------------+

Change-Id: I6ec6dd0a0202119633e594c9a72f361156330b06
Signed-off-by: William Wu <william.wu@rock-chips.com>
 2020-11-11 22:06:40 +08:00
Ren Jianing
3e58c5e6ae arm64: dts: rockchip: rk3568: add pclk_usb for EHCI/OHCI 
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: I168748678867a7f6004bbd0809efd884d8aa9f04
 2020-11-11 21:58:28 +08:00
Ren Jianing
cc488a228c ohci-platform: add the max clock number to 4 
Rockchip SoCs such as RV1126 and RK356x requires
4 clocks to be enabled for OHCI.

Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: Ia5202ca7223d95a4b39b1581f740e03ca3f54224
 2020-11-11 21:58:10 +08:00
Ren Jianing
b9d9feb075 phy: rockchip: inno-usb2: fix some issues for rk3568 usb2 phy 
This patch fixes the following issues for rk3568 usb2 phy.

1. Set utmi opmode to normal mode for rk3568 usb phy when usb
   phy enter suspend mode via usb phy grf. It can help to avoid
   the DM/DP floating and the line state be detected as 2'b11.

2. Fix the offset of INT_STATUS_CLR. It can help to avoid
   triggering the linestate irq constantly.

Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: Iba53e416c44a45baa180ad3abcc91d1d71900158
 2020-11-11 21:58:10 +08:00
Wang Jie
18e6cd9d1e arm64: dts: rockchip: rk3566-tablet: modify sc7a20 device address 
Signed-off-by: Wang Jie <dave.wang@rock-chips.com>
Change-Id: I32bf947268f10173ac5eaa3425a1cc29c5c47f71
 2020-11-11 21:56:56 +08:00
Shawn Lin
3281563e94 PCI: rockchip: dw: Fix support for RK356X platforms 
First we add a 3v3 regulator support, and remove some
fast link settings.

Change-Id: Icf1c854aa06cad664bac77654fb08224af95aedc
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2020-11-11 21:50:57 +08:00
Shawn Lin
bbf7de5ad9 arm64: dts: rockchip: enable pcie20 for rk3568-evb1-ddr4-v10 
Change-Id: I7f0e64f70d9efe86399f6f69600de323f24f8e13
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2020-11-11 21:50:46 +08:00
Shawn Lin
c8a925b706 arm64: rockchip_defconfig: Enable CONFIG_PCIE_DW_ROCKCHIP 
Change-Id: I46e23868688d45810d792bb048930d08c4fb726d
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2020-11-11 19:56:31 +08:00
Shawn Lin
ecdf4148c8 arm64: rockchip_defconfig: Add CONFIG_REGULATOR_GPIO 
Change-Id: I1cb7dee1c593c424c0821e31d3d32c579b11ed0c
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2020-11-11 19:22:06 +08:00
Shawn Lin
1603e4ecf6 arm64: dts: rockchip: rk3568: Fix PCIe30x2 DBI and remove useless clks 
Change-Id: Icae9ef5661b62abc588b3b86ddbd671772d5d5d5
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2020-11-11 19:22:05 +08:00
Finley Xiao
8a65d18577 arm64: dts: rockchip: rk3568: Add pvtm device node 
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Idef95dc6d0da0cc5cbf97d1c4572d8107ee131c9
 2020-11-11 15:21:19 +08:00
Finley Xiao
aec8ff24ff soc: rockchip: pvtm: Add support for RK3568 SoCs 
This adds the necessary data for handling pvtm on the RK3568 SoCs.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ie4499f613d7d3ef2edb11fd6a81d70d699317caf
 2020-11-11 15:21:19 +08:00
Finley Xiao
94ccb804c3 dt-bindings: rockchip-pvtm: Support the RK3568 SoC compatible 
Add a new compatible for thermal founding on RK3568 SoC.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I4a6db880cde95be2d18074efbdef68cb187e50a7
 2020-11-11 15:21:19 +08:00
Algea Cao
cdbb863092 drm: rockchip: dw-hdmi: Enable 3568 hdmi ddc 
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I9dd63de7a98cb70f9e40c7ee82bcfca5884b9232
 2020-11-11 15:21:19 +08:00
Alex Zhao
87649a9e7d arm64: dts: rockchip: rk3566-evb2-lp4x-v10: fix for wifi/bt 
Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Change-Id: I2d8df2776af0c18eff33fbcf8908f89ff2a0a6a9
 2020-11-11 15:21:19 +08:00
Elaine Zhang
f807c08d2b arm64: dts: rockchip: rk3568: setting npll to 1.2G when clk init 
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: If088d432552d186866dd53211c5a2126870f62a4
 2020-11-11 15:21:19 +08:00
Elaine Zhang
75f941d347 clk: rockchip: rk3568: mark npll as critical clock 
npll is for dsu high freq.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I4fd3141e577ee0933d8eac07bd154c1d1b341edd
 2020-11-11 15:21:19 +08:00
Bin Yang
5f0c2578ed usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode 
In the 3.0 device core, if the core is programmed to operate in
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
clock. Enabling this feature allows the pipe3 clock to be not-running
when forcibly operating in 2.0 device mode.

Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Change-Id: I217a380815c21903c1090bd003c1d8ba2fadbe7c
 2020-11-11 12:02:01 +08:00
Shunqing Chen
7ec24c91e0 arm64: dts: rockchip: rk3568: add phy reference clk for hdmi 
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Change-Id: Ie581092df86da7b11c7b7e3651a812a3c8721ac1
 2020-11-11 12:01:03 +08:00