Rockchip RK860X regulators share the exact same functionality and
register layout as the Fairchild FAN53555 regulators.
Therefore extend the driver to add support for them.
Both types use the same vendor id in their ID1 register, so it's not
possible to distinguish them automatically.
Similarly, the types also do not match. Type 8 used by the RK8603
and RK8604 start at 500mV and increment in 6.25mv steps,
while the FAN53555 type 8 starts at 600mV and increments in 10mV steps.
And the en register is also differences.
Change-Id: Id93f85de91b79a1922b1efc27771f30dd7bc8bcb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Since commit 84af7a6194 ("checkpatch: kconfig: prefer 'help' over
'---help---'"), the number of '---help---' has been gradually
decreasing, but there are still more than 2400 instances.
This commit finishes the conversion. While I touched the lines,
I also fixed the indentation.
There are a variety of indentation styles found.
a) 4 spaces + '---help---'
b) 7 spaces + '---help---'
c) 8 spaces + '---help---'
d) 1 space + 1 tab + '---help---'
e) 1 tab + '---help---' (correct indentation)
f) 1 tab + 1 space + '---help---'
g) 1 tab + 2 spaces + '---help---'
In order to convert all of them to 1 tab + 'help', I ran the
following commend:
$ find . -name 'Kconfig*' | xargs sed -i 's/^[[:space:]]*---help---/\thelp/'
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I6c1a95c0cb15b1a5a4215acba748e7023dfd4338
On RV1109/RV1126, there is a rare risk that command would not take effect
for rkvenc_mmu. Rewrite command no more than 10 times. Only consider
enable/disable paging, enable/disable stall these 4 commands
which result can be checked through register RK_MMU_STATUS.
Change-Id: I508783821f05513b28392d5a3d3a55953917f910
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Master fetch data and cpu update page table may work in parallel, may
have the following procedure:
master cpu
fetch dte update page tabl
| |
(make dte invalid) <- zap iotlb entry
| |
fetch dte again
(make dte invalid) <- zap iotlb entry
| |
fetch dte again
(make dte invalid) <- zap iotlb entry
| |
fetch dte again
(make iommu block) <- zap iotlb entry
New iommu version has the above bug, if fetch dte consecutively four
times, then it will be blocked. Fortunately, we can set bit 31 of
register MMU_AUTO_GATING to 1 to make it work as old version which does
not have this issue.
This issue only appears on RV1126 so far, so make a workaround dedicated
to "rockchip,rv1126" machine type.
Change-Id: I808bf87898e2dfdd8ada5666234e4c2c3237ffde
Signed-off-by: Simon Xue <xxm@rock-chips.com>
The default max segment size is 64Kb, if memory that device
want to map larger than default then it will break to several times
mapping which may result in non-contiguous IOVA. So set to 4Gb
Change-Id: I22eb7f30a3f741689c8c32734509c34f99fd8100
Signed-off-by: Simon Xue <xxm@rock-chips.com>
iommu may enabled by pm_runtime_get_sync from vop, this
path is not accept by vop, so ignore device_link for vop
Change-Id: I532a2a964b423e78fadec02c3b4c2952301ebf4b
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Iommu framework introduce default_domain for automatic
attach which we were not interesting before, now rockchip
iommu driver following this way that make things different:
iommu_detach_device function is not able to disable iommu anymore.
It just do following things either:
1. Just return
Like Vcodec/ISP who does not allocate new domain
2. Attach default_domain
Like vop who allocate new domain by vop driver
We have no way to temporary disable iommu,to fix this issue, master
driver need to attach a NULL domain,also master driver need more step:
1. iommu_attach_device(NULL, dev) -> disable iommu
2. iommu_detach_device(NULL, dev) -> attach default_domain
Above two steps must comes in pairs.
Following order called by driver is not permitted:
1. iommu_attach_device(domain, dev)
2. iommu_attach_device(NULL, dev)
3. iommu_detach_device(NULL, dev)
4. iommu_detach_device(domain, dev)
Correct is:
1. iommu_attach_device(domain, dev)
2. iommu_detach_device(domain, dev)
3. iommu_attach_device(NULL, dev)
4. iommu_detach_device(NULL, dev)
Change-Id: I12b1e27e5119fb1abd05ccce57c9e941f03e9498
Signed-off-by: Simon Xue <xxm@rock-chips.com>
When jumping from uboot to kernel, vop may page fault, this due
to vop working parallel to kernel probe dts node by cpu.
Defer vop iommu attach function when iommu_ops->add_device called,
and hand the attach function to vop driver is a solution.
Change-Id: I84822ac7a3d0884f96df774a2363c22cbf0f074a
Signed-off-by: Simon Xue <xxm@rock-chips.com>
When iommu fall into interrupt, status register indicate more information
than read or write flag, so use status register as parameter when callback
report_iommu_fault
Change-Id: I07c6b9996f305eb970bd1d1d2b0f2a7db53cc6ba
Signed-off-by: Simon Xue <xxm@rock-chips.com>
RK3128 and RK3126 failed to read vop iommu register, it is SoC bug.
Add this patch as a workaround for this bug, make SoC work as normal
Change-Id: I44d4ef7f6e15f85a466563b0b3e8e091db23fba0
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Before reboot if the DCDC is disabled,
the DCDC is still disabled after restart.
We have an method to workaround:
Use vsel pin to switch the voltage between value in FAN53555_VSEL0
and FAN53555_VSEL1. If VSEL pin is inactive, the voltage of DCDC
are controlled by FAN53555_VSEL0, when we pull vsel pin to active,
they would be controlled by FAN53555_VSEL1.
In this case, we can set FAN53555_VSEL1 to disable dcdc,
So we can make vsel pin to active to disable dcdc,
VSEL pin is inactive to enable DCDC.
Change-Id: I14c823ed11dc3369044ad2ed0b53a6027acbccd0
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The pins from GPIO2B0 to GPIO2B6 are located at GRF_GPIO2BL_IOMUX,
they are recalculated to get correct iomux.
Change-Id: I1e46697c4508c396b5e8140c32c4185925a040ea
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The main description for rk3308b is as follows:
- Old iomux multiplexing extension;
- GRF_SOC_CON5 register add some bits;
- Newly added GRF_SOC_CON13/15 register.
Change-Id: I94bfcae5387aceae14895f1cafa0bfea51bf8b63
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
There are writable 32 bits for PMU_GPIO0's iomux, so add the
IOMUX_WRITABLE_32BIT to read iomux register at first, it would
not change others' bits.
Change-Id: I1fb27c60d5d26e5719b6911a78e7cdf144feba26
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The origin commit is 'pinctrl: rockchip: Add slew rate support for
px30', this commit only pick the support codes without px30, that will
be supported in another path.
The usage of slew rate is needed to config it at DTS,
such as:
fast speed: slew-rate = <1>;
slew speed: slew-rate = <0>;
Change-Id: Iefa9c15a35c6c1e94f716f5d6dd7e30d20a7293f
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The gpio v2 has some new features:
- Use mask bit for register write;
- Both edge intterupt supported;
- longer debounce time for input intterupt.
Change-Id: I61f3974d2e0cf0e93c686aa11cd35162e59f393b
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
to slove the display shaking, when uboot logo display to kernel show.
Change-Id: I804aa09f24bc4fa7b6314a7a5487f0ee1a321724
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
others clk change it's parent from cpll to dummy_cpll.
the vop's parent just vpll and cpll,
make sure each vop have it's own pll as parent.
Change-Id: Ia61e10918e14a69c053455018ddf0183ff15ea19
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add cru and pmucru regs dump when system panic.
It's just for debug.
Change-Id: I3f837f2941054129d20c2355d86f575d6ee84665
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
These clock rate are used for HDMI display.
Change-Id: I4742dcfe8ddedfa6b86c38ce03bcaa5c28b34c4e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We need to declare that we enable all NOCs which are critical clocks
always and clearly and explicitly show that we have enabled them at
clk_summary.
Change-Id: I859664692b4d1bb0dda0ee38295dfcbc3cc70019
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
There are some clks(uart) that do not have to comply with the 20 times
fractional divider limit.
Change-Id: I420d8ba3b5de65d9e0ea74920d5ea8450ae94465
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add the clock tree definition for the new rk3568 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I9c2282938ec51ddf2dd71390b9b0cfef1f0d2735
