When switching sample rates, the clock settings are as follows:
- For 48K, MCLK = 256fs = 256 * 48K = 12288K
- For 16K, MCLK = 256fs = 256 * 16K = 4096K
- For 8K, MCLK = 256fs = 256 * 8K = 2048K
The `set_sysclk` function in the soc i2s_tdm controller does not
actually perform `clk_set_rate`; it merely passes the parameters.
The actual `clk_set_rate` is called during `i2s_tdm_hw_params`.
However, `rk817_hw_params` performs `restart_clk_apll` inside,
which sets the PLL parameters that do not match the MCLK,
resulting in silence. To resolve this, clk_set_rate for the MCLK
frequency should be called within the set_sysclk function.
Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: I3ad233542a5e8b16ae72f829e086a25f5be4a095
This patch will impact performance, so disable this feature by default.
This reverts commit 980a9f6834.
Change-Id: I8f7e2413049f92e87b4a915e9e597172ecb955ce
Signed-off-by: Liang Chen <cl@rock-chips.com>
According to SPI signal test results:
(1) When using SPI IOs under 3.3V power domain, need to increase
driver strength to level3.
(2) When using SPI IOs under 1.8V power domain, use default driver
strength(level2) is best.
Change-Id: I0404418256d4f9671393345bf44ffd4e285af584
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
1. Prevent data from crossing boundaries
2. Support GPIO_TYPE_V2_2 debounce config
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I57e295806a4f0f4002527daf77fe41f584a7e9e1
mclk pin has been addressed in i2s_8ch_mclk, and used by
codec, so, do not redefine it again in i2s_8ch_bus.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I74a3c3f817142ff4c313bbf9a39ced215f04feb6
1.mipi date rate need to set 1850Mbps
2.DSI RGB output need to set skip first frames
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
Change-Id: I0a339e339bd94dae66be682a4481a4b0cef8ff99
In some manufacturers, we have found that the i2c clk/data
pullup power is disabled when the system is shutdown or suspended,
As a result, the first i2c communication fails when probing
or resuming. Therefore, it is necessary to perform i2c
communication once by default when probing or resuming.
Change-Id: I0819d733ff3a6f9172c1d3bf7b8e5bf72bc52730
Signed-off-by: Weixin Zhou <zwx@rock-chips.com>
For controller which is managed by PD (power-domain),
when PD off, the controller is reset to the default
status, and the FRAC-DIV is a fixed value(1/20).
Once the mclk is enabled, there are some high freq cycle
leak, to fix this issue, we use the pinctrl-idle to
block these cycles until the config has been come back
to the normal state.
Ref: commit 1f8e86a5ea ("ASoC: rockchip: pdm: Fix clk glitch on runtime PM")
Signed-off-by: XiaoTan Luo <lxt@rock-chips.com>
Change-Id: I8b1226896d8ca20293335a879452df732801f712
If "POST_CSC_DATA" property is used to transfer the csc
parameters, it need config the csc registers by the
parameters from "POST_CSC_DATA". Otherwise, It should
config the csc register by the parameters from the
connector bcsh property.
Change-Id: Ia126941d15d4403c6b690fcc6b7937f03ca71951
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
There is a ASYNC bridge between HCLK and SCLK domain.
On AUPLL case, we found RX data shift ahead 1-Bit on
TRCM-TX sometime (0.00x%), but it success on GPLL(50w+).
The root cause:
HCLK Domain: Config the XFER-3, pull up SIGNAL to HIGH.
SCLK Domain: SCLK_RX/TX samples the HIGH level to start.
Because HCLK Domain is async to SCLK Domain, So, there
is a risk that RX samels the HIGH Level, but RX not.
(at the edge XFER from LOW to HIGH)
Solution:
1, Gate the SCLK
2, Config the XFER-3
3, Ungate the SCLK
Thus, TX/RX Always samples the right Level at the same
time.
After this patch, Test passed over 50w+.
Test Script:
#!/bin/sh
count=0
killall aplay
sleep 1
while true
do
yes `echo -en "\x11\x11\x22\x22"` | tr -d '\n' | \
aplay -D hw:2,0 --period-size=1024 --buffer-size=4096 -r 192000 -c 2 -f s16_le &>/dev/null &
sleep 0.1
rxd=`io -4 0xfe470028 | awk '{print $2}'`
echo "[$count]: $rxd"
if [ "$rxd" != "22221111" ]; then
echo "FAIL: mismatch: $rxd, expected: 22221111"
break
fi
count=$((count + 1))
killall aplay
sleep .1
done
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I10258b92d2f62ab36b5ccc55e8bcc752f3af9d4f
Similar to the API clk_gate_endisable.
Can be replaced by API clk_gate_endisable directly
once the symbol exported been merged.
It's workaround for GKI.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I91a53734add53b3156afc2b03b25cdc207822331
Slave Resume Situation:
i2s-tdm acts as slave, and the external device, such as dsp
acts as master.
aplay -D hw:0,0 --period-size=1024 --buffer-size=4096 t.wav &
echo mem > /sys/power/state
the aplay was freeze and system go to sleep.
press the power-key to wakeup system, and now the aplay will
resume playback.
But, there is a case the external dev resume too slow to provide
clk to i2s-tdm, so, we need add a delay to make it resume well.
e.g.
&i2s {
rockchip,resume-deferred-ms = <1000>;
};
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: If9a82c8357cef23bd50305c585ee28794f45d347
VOP aclk freq is very important info for our debug, so add it to
drm dri summary.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Iad97b5b81752e970622f55888fcc4327d2bb4c93
VOP aclk freq is very important info for our debug, so add it to
drm dri summary.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I197e64104c49bd62d85d5dba4b0c4e1763fd62e2
active_vp_mask mask the active vp, and at rk3588 splice mode, vp0 and
vp1 will be mask, it can't indicate display number, so we add the
active_display_mask to record it.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I7bebf21b4d844d92956d6e7427162cdbe694fe7a
userspace maybe want to change some property and commit new frame
without any plane, so we use new api to get current plane or bandwidth
info correctly.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I19c471770abba04429c2e8f35d4bcbc8ea2f87b6
1. Turn off differential receiver in suspend mode for
the otg0 and otg1 port to save power consumption.
2. Set otg0 and otg1 port HS eye height to 425mv.
3. Choose the Tx fs/ls data as linestate from TX driver
for otg0 and otg1 port to improve fs/ls devices
compatibility with long cable.
Change-Id: I60468354b7903016b4f35c6b394035adc077b960
Signed-off-by: Jianwei Zheng <jianwei.zheng@rock-chips.com>
Test on RK3576 EVB1/Tablet connected with Type-C to HDMI
cable, it is easy to trigger kernel panic during system
enter/exit deep sleep with the following log:
[ 100.859203][ T3862] PM: PM: Pending Wakeup Sources: NETLINK
[ 100.874736][ T3862] PM: Some devices failed to suspend, or early wake event detected
[ 100.984288][ T3862] rockchip-usbdp-phy 2b010000.phy: trsv ln0 mon rx cdr lock timeout
[ 100.989921][ T3893] xhci-hcd xhci-hcd.6.auto: xHC error in resume, USBSTS 0x411, Reinit
[ 100.989936][ T3893] usb usb1: root hub lost power or was reset
[ 100.989946][ T3893] ub usb2: root hub lost power or was reset
[ 100.990852][ C3] SError Interrupt on CPU3, code 0x00000000bf000002 -- SError
[ 100.990862][ C3] CPU: 3 PID: 3895 Comm: kworker/u16:18 Tainted: G
[ 100.990868][ C3] Hardware name: Rockchip RK3576 TABLET V10 Board (DT)
[ 100.990871][ C3] Workqueue: events_unbound async_run_entry_fn
[ 100.990886][ C3] pstate: 804000c5 (Nzcv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 100.990891][ C3] pc : local_daif_inherit+0xc/0x10
[ 100.990898][ C3] lr : el1_abort+0x2c/0x5c
[ 100.990905][ C3] sp : ffffffc014973650
......
[ 100.990969][ C3] Kernel panic - not syncing: Asynchronous SError Interrupt
[ 100.990973][ C3] CPU: 3 PID: 3895 Comm: kworker/u16:18 Tainted: G
[ 100.990978][ C3] Hardware name: Rockchip RK3576 TABLET V10 Board (DT)
[ 100.990980][ C3] Workqueue: events_unbound async_run_entry_fn
[ 100.990988][ C3] Call trace:
[ 100.990990][ C3] dump_backtrace+0xf4/0x118
[ 100.990996][ C3] show_stack+0x18/0x24
[ 100.991000][ C3] dump_stack_lvl+0x60/0x7c
[ 100.991005][ C3] dump_stack+0x18/0x38
[ 100.991010][ C3] panic+0x16c/0x388
[ 100.991014][ C3] nmi_panic+0xa4/0xa8
[ 100.991019][ C3] arm64_serror_panic+0x6c/0x94
[ 100.991025][ C3] do_serror+0xc4/0xd0
[ 100.991029][ C3] el1h_64_error_handler+0x34/0x48
[ 100.991034][ C3] el1h_64_error+0x68/0x6c
[ 100.991038][ C3] local_daif_inherit+0xc/0x10
[ 100.991044][ C3] el1h_64_sync_handler+0x54/0x90
[ 100.991049][ C3] el1h_64_sync+0x68/0x6c
[ 100.991053][ C3] readl+0x44/0x8c
[ 100.991059][ C3] xhci_set_port_power+0x8c/0xcc
[ 100.991066][ C3] xhci_hub_control+0xb7c/0x19b8
[ 100.991071][ C3] usb_hcd_submit_urb+0x688/0x9b8
[ 100.991079][ C3] usb_submit_urb+0x480/0x4f4
[ 100.991084][ C3] usb_start_wait_urb+0x6c/0x110
[ 100.991089][ C3] usb_control_msg+0xc4/0x144
[ 100.991093][ C3] hub_activate+0x374/0xa1c
[ 100.991099][ C3] hub_reset_resume+0x18/0x2c
[ 100.991105][ C3] usb_resume_both+0x218/0x32c
[ 100.991110][ C3] usb_resume+0x28/0x7c
[ 100.991115][ C3] usb_dev_resume+0x14/0x24
[ 100.991121][ C3] dpm_run_callback+0x64/0x230
[ 100.991128][ C3] __device_resume+0x1c8/0x360
[ 100.991133][ C3] async_resume+0x24/0x3c
The root cause is that the source clock of the usb xHCI
maybe changed during system suspend and wakeup.
1. When plug in Type-C to HDMI cable which support DP
4*lanes + USB2.0, the usbdp phy driver call the
udphy_u3_port_disable() to disable u3 port and select
the utmi clock which from usb2 phy for usb xHCI source
clock.
2. During system wakeup, the Type-C CC state maybe changed
and the Type-C subsystem will call the udphy_orien_sw_set()
to reinit the udphy->mode as DP 2*lanes + USB3.0.
3. In the system pm resume process, the usb controller driver
call the rockchip_u3phy_init() to initialize the usbdp phy.
Because the udphy->mode has been modified to UDPHY_MODE_USB,
so it call udphy_u3_port_disable() to enable u3 port and
select the pipe clock which from usbdp phy for usb xHCI
source clock.
4. In udphy_init(), it waits for rx cdr lock timeout, which
means that the usb3 phy and its pipe clock are not ready.
5. Later in the usb_dev_resume(), the xHCI driver trigger
kernel panic when access the xHCI controller register
because its source clock isn't ready.
To fixes this issue, the patch disable u3 port and select
the utmi clock for usb controller if wait rx cdr lock timeout.
Change-Id: I3213c59dc9f0bb183037c943c6adaf769def194e
Signed-off-by: William Wu <william.wu@rock-chips.com>
Fixes: e6dfeb296d ("Revert "clk: fractional-divider: check parent rate only if flag is set"")
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: Ia287357af26437f525c74104b4fd5b20f4ec2f16
Commit 33629d3509 ("ata: ahci: Add DWC AHCI SATA controller support")
move snps,dwc-ahci support from ahci_platform.c to ahci_dwc.c.
So replace CONFIG_SATA_AHCI_PLATFORM by CONFIG_AHCI_DWC.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I04182b5b98f58457c3784fbca4fc784e3a36e0ee
Commit 33629d3509 ("ata: ahci: Add DWC AHCI SATA controller support")
move snps,dwc-ahci support from ahci_platform.c to ahci_dwc.c.
So replace CONFIG_SATA_AHCI_PLATFORM by CONFIG_AHCI_DWC.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I501471934fea6645da3bb7a1a592715856d02fa2
We usually need to write vop regs for debug, but this depend on io cmd
and devm,
they are often forget to be enabled, so we add this node to instead of
it:
you can use the following cmd to update VOP regs:
echo offset val > /sys/kernel/debug/dri/0/video_portx/regs_write
the video_portx is depend on hardware config, you can get this info
from the cmd:
cat /sys/kernel/debug/dri/0/summary
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I687ecc44dc638bfdf770983f96ce7b5470ff3691
rockchp drm debug include dump buffer, show color bar and regs write,
only dump buffer need to depend on no gki, the others can be enabled
at gki firmware.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I715c1000d9dd29c915632d6a54706008440d0cdb
NV20 and NV30 is supported by drm core, so no need to depend on
CONFIG_NO_GKI.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I21c7ed5741ea89da6999f38b37d3a248699385fd
