Provide the dynamic power coefficient of the big and little CPU
clusters. These numbers are currently in use on the Samsung Chromebook
Plus ("Kevin").
The power allocator thermal governor doesn't know how to do anything if
it doesn't get power parameters from its cooling devices (in this case,
CPUfreq). So this effectively enables the power-allocator governor.
Signed-off-by: Brian Norris <briannorris@chromium.org>
[set the property in each core node]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(Cherry-picked from f4697bd702)
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Conflicts:
arch/arm64/boot/dts/rockchip/rk3399.dtsi
Change-Id: I8899a2224fe6cbf6e6f874006bf115eee62b7041
Patch reorder some codes to sync with upstream codes
Change-Id: Iba1971dcee9b5cfb25b62e8bfa2135f0576398e9
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Clean up the init code and move the creation of factor clocks to the
appropriate positions coming from the clock architecture diagrams.
This also unifies the artificial separation of the hclk_vcodec etc clocks
again.
We do keep the separate definition of some watchdog and usb480m pseudo
clocks for now, as they're not real factor clocks from the clock-tree
but placeholders for fixes to come (usb480m gets supplied by the
missing driver for the new usbphy type and the watchdog-gate is sitting
somewhere else together which we cannot model currently).
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 36714529f8)
Change-Id: I43b579b4d0b16b191e220a1748b6d11c7a30b4be
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
rockchip_clk_register_ddrclk should not return NULL when failing
to call clk_register, otherwise rockchip_clk_register_branches
prints "unknown clock type". The actual case is that it's a known
clock type but we fail to register it, which may makes user confuse
the reason of failure. And the pr_err here is pointless as
rockchip_clk_register_branches will also print the similar message.
Change-Id: Id09f496979ab839d04b5ec4cf5c623fde9215440
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 4a262b14c5)
camera: rockchip: add sensor ioctl and max gain.
1. add RK_VIDIOC_SENSOR_CONFIGINFO;
2. add RK_VIDIOC_SENSOR_REG_ACCESS;
3. add max_exp_gain_h/max_exp_gain_l;
camera: rockchip: merge isp11: rockchip: v0.1.7
isp11: rockchip: v0.1.7
1. Direct config isp lsc table size in cifisp_lsc_config.
Because active_lsc_width is not same with isp register
after isp reset.
2. Support separate config sensor gain and shutter time
for some sensor which gain and shutter isn't valid at
the same time. for example ov2710.
ov4689:v0.1.0;
ov2710:v0.1.1;
imx323:v0.1.0;
camera: rockchip: Support v4l2 subdev api
ov2710: v0.1.2
ov4689: v0.1.1
imx323: v0.1.2
camera: rockchip: add lock for stream/aec
hold reg in AEC will affect stream reg, if asynchronous.
camera: rockchip: fix sensor timing
if fps changed, vts changed, update to timing.
camera: rockchip: support set flip api
camera: rockchip: support get flip api
camera: rockchip: fix release bug
should be free pdata at the end
camera: rockchip: imx323
fix s_fmt failed for imx323 v0.1.2;
camera: rockchip: fix s_frame_interval failed
fix s_frame_interval failed when frame interval is match
active config frame interval.
camera: rockchip: imx,aptina,ov
Check xxx_camera_module_init return value in PLTFRM_CIFCAM_ATTACH
camera: rockchip: release sensor if init fail
camera: rockchip: imx,aptina,ov
support mirror/flip conifg in dts for imx323/ov4689
camera: rockchip: add s_frame_interval/g_frame_interval
camera: rockchip: ov, aptina, imx
add s_frame_interval/g_frame_interval
camera: rockchip: imx,ov,aptina
1.imx,ov: fix g_timing error if s_frame_interval before stream_on,
because vts_cur is update in stream_on;
2.aptina: fix compile error;
camera: rockchip: imx,ov,aptina
1. fix calc vts wrong in xxx_camera_module_s_stream
Change-Id: I5a6e75f2ce3c50d69c51af9792232c60b6982128
Signed-off-by: Hu Kejun <william.hu@rock-chips.com>
clk_testout1 and clk_testout2 are used for camera handling, so add their ids.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 25fb42b1cf)
Change-Id: I8000e84264b032835cc3d11a6810264967f4248e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
we use SCLK_TESTCLKOUT1 and SCLK_TESTCLKOUT2 for camera, so add those ids.
Signed-off-by: Eddie Cai <eddie.cai.linux@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit f22e4359cd)
Change-Id: Ibbdb8e9dabd8c955ef3745c0f49c20f4c763e870
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Export the dclk_vop_frac out, so we can set the dclk_vop as the
child of dclk_vop_frac, and then we can start to take use of
the fractional dividers.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 7b0f9e357a)
Change-Id: I08686f8ecbcfb5de7bc99aadd314f6e35ac22995
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Export the dclk_vop_frac out, so we can set the dclk_vop as the
child of dclk_vop_frac, and then we can start to take use of
the fractional dividers.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit e33075db73)
Change-Id: I3d47c6aecc338de45b48414f0d0327c17e6d2b15
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Currently the fractional divider clock time can't handle the
CLK_SET_RATE_PARENT flag. This is because, unlike normal dividers,
there is no clk_divider_bestdiv() function to try speeding up the parent
to see if it helps things.
Eventually someone could try to figure out how to make fractional
dividers able to use CLK_SET_RATE_PARENT, but until they do let's not
confuse the common clock framework (and anyone using it) by setting the
flag.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 29edeccb44)
Change-Id: Ic7fa067ed80767c937dd9c8506d2d1e86ee1c93a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We need to get the accurate 533.25MHz for the DP display.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 5c1c63f634)
Change-Id: Ib945c80451d52081683488fe410c5200622fb1c3
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Usually, the 800MHz and 1GHz are supplied for CPLL and NPLL in the RK3399.
But dues to the carelessly copying from RK3036 when the RK3399 bringing up,
the refdiv == 6, it will increase the lock time, and it is not an optimal
configuration.
Let's fix them for the lock time and jitter are lower:
800 MHz:
- FVCO == 2.4 GHz, revdiv == 1.
1 GHz:
- FVCO == 3 GHz, revdiv == 1.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 1dfbec3905)
Change-Id: I725e8cb542afa7caf7cbb5ff6f747f65d48c5ced
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The PMU Cortex M0 on rk3399 is intended to be used for things like
DDRFreq transitions, suspend/resume, and other things that are the
purview of ARM Trusted Firmware and not the kernel. As such, the
kernel shouldn't be messing with the clocks. Add CLK_IGNORE_UNUSED to
these clocks.
Without this change, the following was observed on a Chromebook with a
rk3399 (using not-yet-upstream ARM Trusted Firmware code and
not-yet-upstream kernel code based on kernel-4.4):
1. We init the clock framework.
2. We start up "DDRFreq", which causes ATF to occasionally fire up the
M0 for transitions. Each time ATF fires up the M0 it will turn on
these clocks and each time it is done it will turn them off.
3. We finally get to the the part of the kernel that calls
clk_disable_unused() and we disables the clocks.
You can see the race above. Basically everything is fine as long as
ARM Trusted Firmware isn't starting up the M0 at exactly the same time
that the kernel is disabling unused clocks. ...but if the race
happens then we go boom.
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 60aadea57e)
Change-Id: I2a78c74edc9bc5d5b4f26224ebdb34eb83afb022
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We need this rate to generate 100, 200, and 228.57MHz from the same
PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
an external display.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked from commit 4ee3fd4abe)
Change-Id: I118c877882d694b358697470225d8d94cb1271b5
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
There is a bit of headphone pop during power on, we
need to increase delay time (200us per loop step).
It looks fine that it may take 200us*128=25.6ms here.
Change-Id: Idbc5b235fd55c26cd71f4693cce98fccce60368f
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
rk3326 and other platform power management implementation
Change-Id: I34b9c773cfee1e684e833cdbcf687ac54cd8d88a
Signed-off-by: Zhang Yunlong <dalon.zhang@rock-chips.com>
The f_blocks of statfs include file system overhead，it is not normal
usage of Posix.
Change-Id: If481626b08c05290626938586e2dc721690f1a91
Signed-off-by: Cliff Chen <cliff.chen@rock-chips.com>
Add usic node for rk3399 USB 2.0 EHCI controller
with usic phy.
Change-Id: Ibb4179ff1479816daa3b8455b0229f8a7a05bbdf
Signed-off-by: William Wu <william.wu@rock-chips.com>
Some EHCI controllers use usic phy (e.g rk3399/rk3288),
in order to enable these controllers, we need to set
some additional EHCI vendor-specific registers.
Support this feature in device tree when using the ehci
platform driver by adding a new property for it.
Change-Id: I279ccfdb5866df49828825bfd41b39fcd58a2832
Signed-off-by: William Wu <william.wu@rock-chips.com>
During dwc3 resume, it shoudn't reset otg controller logic
if device is connecting with the otg port, because it will
cause device to be reenumerated. More seriously, it may
cause the otg_work to enter disconnect process and power
down usb3 controller power domain, at the same time, if
the xHCI driver is accessing the controller asynchronously,
it will cause system hang.
Change-Id: Id546277bd4082b7baeff830788643a800330ae8e
Signed-off-by: William Wu <william.wu@rock-chips.com>
When do core init, only reset the core for device mode.
Becasue in host mode, xHCI driver will reset the core
and its host block via usbcmd.hcrst. If we do core reset
in dwc3_core_init() for host mode, it will reset both
the dwc3 core registers and xHCI registers, and cause
device to be reenumerated when usb suspend/resume.
Change-Id: If723ce8a771975e9757d28cb2c114d6269581677
Signed-off-by: William Wu <william.wu@rock-chips.com>
By default, only using lrck_tx for PCM by hardware,
therefore, we need to use I2S_CKR_TRCM_TXONLY.
Change-Id: I6c4077e7e7e65b8a3a21416fd61d5900b3b72f42
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
This patch using PCM rising late1 and slave mode for
Bluetooth HFP.
Change-Id: I4a0188134d7d0ef0690c6c7c9f94fc8ec50c1671
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
If there is only one lrck (tx or rx) by hardware, we need to
use 'rockchip,clk-trcm' specify which lrck can be used.
Change-Id: I3bf8d87a6bc8c45e183040012d87d8be21a4c133
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
