Add the clock tree definition for the new RV1126B SoC.
Change-Id: Id03fb5d02c59fc2f4a55e0a9b7a98692a049d6bf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add the dt-bindings header for the rv1126b, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rv1126b.
Change-Id: I565399bb3a338453c6f2f3ac5d79775ad2be9481
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
All hdmi 2.1 contents in the edid are saved in this
struct.
Change-Id: I2400fb9fe77163667419677ca3f55e88d795d2be
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
The HDMI spec 10.3.2 talks about SCDS, Sink Capability Data
Structure, exposed via HF-VSDB or HF-SCDB. The actual content
of the them is same. So it needs only one parse function.
Change-Id: I61459b6d21d7e0666c1561bb2ad41729e0d00a49
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
When assign the vp dclk parent as hdmi phy pll in dts. The
vp dclk parent should get by clk_get_parent. The vp.dclk_parent
is not the real parent.
Change-Id: I4b1ba1e1b46e2f5db323069402c4b322ba4a836f
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
1.Determine whether to enable dsc based on the current resolution
and color format.
2.Determine the dsc format of the output according to the
capability of sink.
Change-Id: If7a1c88ea1b6ec0208c9dc9d91a56376ff656707
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
When the dsc bpp is less than 9, hdmi output will flash on TV.
It is speculated that the reason is that pixel rate of sink
decoding is not enough.
Taking 8bpp as an example, dsc clk needs to be 1/3 of the input
clk.the theoretical calculation of DEN compression 1/3, at this
time, the clk of vop dsc to hdmi tx can be reduced to about 260M
to meet the 8bpp transmission.
RK3588 dsc clk only supports 1/2 frequency division, so dsc clk
is 1/2 input clk, which needs to increase blank, which is
equivalent to compressing the absolute DEN time. TV is likely to
decode at a decoding rate of around 260M. DEN absolute time
shortening results in abnormal TV decoding.
So the value of hblank needs to be reduced when bpp is below 9.
The measurement can be displayed normally on TV, but reducing
the hblank will result in non-standard timing of the hdmi output.
This may cause compatibility issues and hdmi cts certification
may fail.
Change-Id: I6cd7890c62980c29322c437b20fb048fe0acbae3
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
In order to cover more application scenarios, when the crtc changes,
the old output_if should be cleared, rather than when the flag
&drm_crtc_state.active_changed is set to 1.
In addition, it would be more reasonable to name new crtc to 'new_crtc'
rather than 'crtc'.
Change-Id: I6821e85b0b6f1152cea3057ebb6f3ec9b821ebee
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
In order to cover more application scenarios, when the crtc changes,
the old output_if should be cleared, rather than when the flag
&drm_crtc_state.active_changed is set to 1.
In addition, it would be more reasonable to name new crtc to 'new_crtc'
rather than 'crtc'.
Change-Id: I5376c44eb5deab75acdbae95782cc5de2e2757d5
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Replace the rockchip_dp_drm_get_new_crtc() by the existing function
drm_atomic_get_new_crtc_for_encoder(), which defined in common Rockchip
DRM driver file 'drivers/gpu/drm/rockchip/rockchip_drm_drv.c'.
Change-Id: I011dc70b5e7e927a201c80cc8ecb15dbef446631
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
struct mutex commit_lock is only used by kernel 4.19,
use ovl_lock now.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Id7eb81fac31026956eeb9b8799b7d8281e4de4c2
For some platforms, such as RK3576, use the win scale instead
of the post scale to configure overscan parameters, because the
sharp/post scale/split functions are mutually exclusice.
Change-Id: If422749ed8defc553924f14f24ab173913b2dcad
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
VPLL is initialized at uboot for dclk, If kernel assigned VPLL clk rate
and different with uboot set rate, this will lead to VPLL reinitialized
and lead to splash screen.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I501bf982b6016841ea046325d692aee73618357b
If only one VP is enabled and the plane mask is not assigned in DTS, all
main windows will be assigned to the enabled VPx, and all splice windows
will be assigned to the VPx+1, in order to ensure that the splice mode
work well.
Fixes: a3d2c5d99a ("drm/rockchip: vop2: fix the default plane_make configurations for RK3588")
Change-Id: I37905fb2d2f186f0da503e0cd410a7f620e34bb1
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
If the plane mask and primary plane both are assigned in DTS, the
primary plane should be included in the plane mask of VPx.
Change-Id: Ie282782aa6f71a177fd61b507893b256261d4dc3
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
It makes sense to check whether the assigned cursor plane can be
attached to a specific VP, as there may be an invalid DTS assignment
for 'cursor-win-id'.
The logs may be like:
......
[ 2.178737][ T81] rockchip-vop2 27d00000.vop: [drm:vop2_create_crtc] *ERROR* Assigned cursor plane: Esmart3 can not attach to VP0
[ 2.178753][ T81] [drm] failed to init cursor plane for vp0
[ 2.178823][ T81] rockchip-vop2 27d00000.vop: [drm:vop2_create_crtc] *ERROR* Assigned cursor plane: Esmart2 can not attach to VP1
[ 2.178838][ T81] [drm] failed to init cursor plane for vp1
......
Change-Id: If18c4db1e8b295e72dae0c23bd0dd41203c4e3ac
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
RK3528/RK3562/RK3576 use the VOP3 architecture, which supports
flexible switching of planes between different VP. User can switch
planes between different CRTCs based on the &drm_plane.possible_crtcs
in userspace, and the plane-mask does not need to be assigned by
default in DTS.
However, for some Linux systems, there may still be scenarios where
it is necessary to specify the primary and cursor planes specifically
used on a VP.
Therefore, the valid plane-mask assignment will change the
&drm_plane.possible_crtcs and establish a fixed binding relationship
between planes and CRTCs, which means that the flexible switching of
planes is not available in the case.
Change-Id: I156f71ceb238c5945a92f48c0024f398711ea811
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Adds the proper MODULE_IMPORT_NS(DMA_BUF) line to the file to get it to
build properly.
Fixes: 5452a06eed ("usb: gadget: uvc: support zero copy with rockchip encoder")
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Iab7fe8977389cd7b3e624a231011ea07d7b6d936
Add const qualifier to rockchip_drm_driver for immutability and safety.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I9d461c702432cf976a0c1413ae1c257faf405f10
The DP_EDP_CONFIGURATION_SET should be configured instead of the
DP_LANE_COUNT_SET register to disable ASSR.
Fixes: 3ae279210e ("drm/bridge: analogix_dp: add support for ASSR mode")
Change-Id: I1dc36bd3dbfdeb09cde761c6905e22feba52558a
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
