The utmi clk is provided by the USB PHY for the USB controller.
And the utmi clk is disabled if the USB PHY enter suspend mode.
The current charge detection sets the USB PHY in suspend mode
at first, then take about hundreds of milliseconds to do charge
detection, in other words, the utmi clk will be disabled hundreds
of milliseconds. It may cause the USB controller work abnormally
during the charge detection.
Actually, the conditions for charger detection is:
1. Set the utmi_opmode in non-driving mode.
2. Set the utmi_xcvrselect to FS speed.
3. Set the utmi_termselect to FS speed.
4. Enable the DP/DM pulldown resistor.
This patch adds a new chg_mode to set the PHY in charge detection
mode according to the above conditions, and set the PHY in normal
mode to keep the utmi clk at the same time.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I1cbf565d5145bdae5bc91132bc5fbff23a5cc443
DSC registers can only be accessed after DSC_PD
power on.
We don't want to power on PD at vop_initial.
We will enable PD when a corresponding module
is enabled.
And enable all PD at vop_inital make it more
complicated for the nest pd(PD_CLUSTER0/1/2/3)
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I362ace6837b24a0ebed5b8486c4ba46680d0e693
HDMI on rk3588 have a inverted V/HSYNC polarity than
other platform.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I84fc369c211a6f8715c77421c0938fe05516fca6
This is the Linux device driver released for RealTek RTL8168B/8111B,
RTL8168C/8111C, RTL8168CP/8111CP, RTL8168D/8111D, RTL8168DP/8111DP,
and RTL8168E/8111E Gigabit Ethernet controllers with PCI-Express interface.
Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Change-Id: I54634ade9602706d1230bb2551f1da7157943814
1.version: 101.10.361.11 (wlan=r892223-20210630-1)
2.both wifi5 and wifi6 are supported
Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Change-Id: Ia0724ebc628ba40afed947275d34ff5c47a410b4
of_iomap allowed to map the same address repeatedly.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I670e2f3ed564c159eed825bc388f4a9ae3a65f76
Reorder system heap pages by bit[14:12] of pages' physical address, it
benefit for dram do access in different banks once time.
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I686c9e54f456d3b7f373ab1b0586125e70f891ec
Two axi bus:
AXI0 is a read/write bus with a higher performance.
AXI1 is a read only bus.
Every window on a AXI bus must assigned two unique
read id(yrgb_id/uv_id, valid id are 0x1~0xe).
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I867df219797da33f89fec6fba639bcdf55cb54b3
Support the system_heap to allow cpu access partial dma-buf.
Change-Id: I8250c0bb26b776b8c8f5e4c3ee0cb71e26445743
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Add DMA_BUF_IOCTL_SYNC_PARTIAL support for user to sync dma-buf with
offset and len.
Change-Id: I03d2d2e10e48d32aa83c31abade57e0931e1be49
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Bt command think if EL0_SP is less than 0xffffffcxxxxxxxxx
it is user mode, but EL0_SP may be 0xffffff8xxxxxxxxx.
According to ARM-V8, the virtual address bit63 determine
TTBR0 OR TTBR1. So if EL0_SP is less than 0x8000000000000000,
it is user mode.
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: Ib97b405df6e669e3806161c97801847e2f5d247a
The controller must route to the comboPHY when it works.
pcie1l0_sel
Select the signal form PHY to PCIe1l0
1'b0: Select comb PHY
1'b1: Select PCIE3 PHY
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I5e7faf71fdd22958c757f884f75ec9a00aeb2fb9
Add dts decode to support the pcie2x1l0 and pcie2x1l1 setting, which is
in PHP_GRF_PCIESEL_CON.
pcie1l0_sel
Select the signal form PHY to PCIe1l0
1'b0: Select comb PHY
1'b1: Select PCIE3 PHY
Usage in dts:
rockchip,pcie1ln-sel-bits = <0x100 0 0 0>;
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I5fb177f37b23c5f3cdaadf8c103f8e6487ea6a76
Currently, the datasheet and pcb design has removed all the
pin {bclk, lrck}_rx, and use the pin {bclk, lrck}_tx only
to simpilify design.
- Remove pin {bclk, lrck}_rx
- Rename pin {bclk, lrck}_tx to [bclk, lrck]
So, we do the same thing by default.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ide90500b766fa39d6f032b0edf309e001939b579
Currently, the datasheet and pcb design has removed all the
pin {bclk, lrck}_rx, and use the pin {bclk, lrck}_tx only
to simpilify design.
- Remove pin {bclk, lrck}_rx
- Rename pin {bclk, lrck}_tx to [bclk, lrck]
So, we do the same thing by default.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ief06364337ccd6b7f2bc61ffd4aeb8d6e168a8a4
Enable the ELAN touch panel used on Rockchip RK3588s tablet.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ia93230ac356752600ea98182cc0b26ae4320c094
drivers/input/touchscreen/elan/elan_update.c:40:22: error: incomplete definition of type 'struct i2c_client'
Fixes: 7f61b3481d ("input: touchscreen: support ELAN TP_5515")
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I9b5aa8c8fc5d6ee2082938dc74719a2db9041f9d
