Commit Graph

860164 Commits

Author SHA1 Message Date
Finley Xiao
0d652a751c dt-bindings: rockchip-thermal: Support the RK3568 SoC compatible
Add a new compatible for thermal founding on RK3568 SoC.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I5ec192a380ffb331120fa0fed20df83d5d83e8d9
2020-11-12 10:14:08 +08:00
Andy Yan
a83c953054 drm/rockchip: vop2: Show plane dump information better
Change-Id: Id86d8805034e64be9c5008321941d0947b93c506
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2020-11-12 09:13:42 +08:00
Simon Xue
bdbd6ca828 iommu/rockchip: fix v2 domain free
Change-Id: I73108579bada8389d36a8d4a60d9a12e81ed718a
Signed-off-by: Simon Xue <xxm@rock-chips.com>
2020-11-11 22:08:55 +08:00
William Wu
fefd47dc10 usb: dwc3: core: only set DEV_FORCE_20_CLK_FOR_30_CLK for high speed
Fixes: 5f0c2578ed ("usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode")
Change-Id: I7082d996979c4f52f898403e25853644e956cf48
Signed-off-by: William Wu <william.wu@rock-chips.com>
2020-11-11 22:06:46 +08:00
William Wu
096abe6464 phy: rockchip: naneng-combphy: select pipe to controller for rk3568
RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers
share one pipe interface for each combo phy, here is the diagram of
the complex connection. This patch select the pipe to the corresponding
controller when set phy mode.

+----------------+
|                |     +------+
| USB3 OTG CTRL0 |---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY0 |
+----------------+     |      |     |            |
|                |     |      |     +------------+
|   SATA CTRL0   |---->|      |
|                |     +------+
+----------------+

+----------------+
|                |     +------+
| USB3 HOST CTRL1|---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY1 |
+----------------+     |      |     |            |
|                |---->|      |     +------------+
|   SATA CTRL1   |  -->|      |
|                |  |  +------+
+----------------+  |
                    |
+----------------+  |
|                |  |  +------+
|  QSGMII CTRL   |---->|      |
|                |     |      |     +------------+
+----------------+     | PIPE |     |            |
                       | MUX  |---->| Combo PHY2 |
+----------------+     |      |     |            |
|                |---->|      |     +------------+
|   SATA CTRL2   |  -->|      |
|                |  |  +------+
+----------------+  |
                    |
+----------------+  |
|                |  |
|  PCIe2 1-Lane  |---
|                |
+----------------+

Change-Id: I6ec6dd0a0202119633e594c9a72f361156330b06
Signed-off-by: William Wu <william.wu@rock-chips.com>
2020-11-11 22:06:40 +08:00
Ren Jianing
3e58c5e6ae arm64: dts: rockchip: rk3568: add pclk_usb for EHCI/OHCI
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: I168748678867a7f6004bbd0809efd884d8aa9f04
2020-11-11 21:58:28 +08:00
Ren Jianing
cc488a228c ohci-platform: add the max clock number to 4
Rockchip SoCs such as RV1126 and RK356x requires
4 clocks to be enabled for OHCI.

Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: Ia5202ca7223d95a4b39b1581f740e03ca3f54224
2020-11-11 21:58:10 +08:00
Ren Jianing
b9d9feb075 phy: rockchip: inno-usb2: fix some issues for rk3568 usb2 phy
This patch fixes the following issues for rk3568 usb2 phy.

1. Set utmi opmode to normal mode for rk3568 usb phy when usb
   phy enter suspend mode via usb phy grf. It can help to avoid
   the DM/DP floating and the line state be detected as 2'b11.

2. Fix the offset of INT_STATUS_CLR. It can help to avoid
   triggering the linestate irq constantly.

Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: Iba53e416c44a45baa180ad3abcc91d1d71900158
2020-11-11 21:58:10 +08:00
Wang Jie
18e6cd9d1e arm64: dts: rockchip: rk3566-tablet: modify sc7a20 device address
Signed-off-by: Wang Jie <dave.wang@rock-chips.com>
Change-Id: I32bf947268f10173ac5eaa3425a1cc29c5c47f71
2020-11-11 21:56:56 +08:00
Shawn Lin
3281563e94 PCI: rockchip: dw: Fix support for RK356X platforms
First we add a 3v3 regulator support, and remove some
fast link settings.

Change-Id: Icf1c854aa06cad664bac77654fb08224af95aedc
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2020-11-11 21:50:57 +08:00
Shawn Lin
bbf7de5ad9 arm64: dts: rockchip: enable pcie20 for rk3568-evb1-ddr4-v10
Change-Id: I7f0e64f70d9efe86399f6f69600de323f24f8e13
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2020-11-11 21:50:46 +08:00
Shawn Lin
c8a925b706 arm64: rockchip_defconfig: Enable CONFIG_PCIE_DW_ROCKCHIP
Change-Id: I46e23868688d45810d792bb048930d08c4fb726d
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2020-11-11 19:56:31 +08:00
Shawn Lin
ecdf4148c8 arm64: rockchip_defconfig: Add CONFIG_REGULATOR_GPIO
Change-Id: I1cb7dee1c593c424c0821e31d3d32c579b11ed0c
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2020-11-11 19:22:06 +08:00
Shawn Lin
1603e4ecf6 arm64: dts: rockchip: rk3568: Fix PCIe30x2 DBI and remove useless clks
Change-Id: Icae9ef5661b62abc588b3b86ddbd671772d5d5d5
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2020-11-11 19:22:05 +08:00
Finley Xiao
8a65d18577 arm64: dts: rockchip: rk3568: Add pvtm device node
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Idef95dc6d0da0cc5cbf97d1c4572d8107ee131c9
2020-11-11 15:21:19 +08:00
Finley Xiao
aec8ff24ff soc: rockchip: pvtm: Add support for RK3568 SoCs
This adds the necessary data for handling pvtm on the RK3568 SoCs.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ie4499f613d7d3ef2edb11fd6a81d70d699317caf
2020-11-11 15:21:19 +08:00
Finley Xiao
94ccb804c3 dt-bindings: rockchip-pvtm: Support the RK3568 SoC compatible
Add a new compatible for thermal founding on RK3568 SoC.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I4a6db880cde95be2d18074efbdef68cb187e50a7
2020-11-11 15:21:19 +08:00
Algea Cao
cdbb863092 drm: rockchip: dw-hdmi: Enable 3568 hdmi ddc
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I9dd63de7a98cb70f9e40c7ee82bcfca5884b9232
2020-11-11 15:21:19 +08:00
Alex Zhao
87649a9e7d arm64: dts: rockchip: rk3566-evb2-lp4x-v10: fix for wifi/bt
Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Change-Id: I2d8df2776af0c18eff33fbcf8908f89ff2a0a6a9
2020-11-11 15:21:19 +08:00
Elaine Zhang
f807c08d2b arm64: dts: rockchip: rk3568: setting npll to 1.2G when clk init
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: If088d432552d186866dd53211c5a2126870f62a4
2020-11-11 15:21:19 +08:00
Elaine Zhang
75f941d347 clk: rockchip: rk3568: mark npll as critical clock
npll is for dsu high freq.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I4fd3141e577ee0933d8eac07bd154c1d1b341edd
2020-11-11 15:21:19 +08:00
Bin Yang
5f0c2578ed usb: dwc3: core: do not use 3.0 clock when operating in 2.0 mode
In the 3.0 device core, if the core is programmed to operate in
2.0 only, then setting the GUCTL1.DEV_FORCE_20_CLK_FOR_30_CLK makes
the internal 2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe)
clock. Enabling this feature allows the pipe3 clock to be not-running
when forcibly operating in 2.0 device mode.

Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Change-Id: I217a380815c21903c1090bd003c1d8ba2fadbe7c
2020-11-11 12:02:01 +08:00
Shunqing Chen
7ec24c91e0 arm64: dts: rockchip: rk3568: add phy reference clk for hdmi
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Change-Id: Ie581092df86da7b11c7b7e3651a812a3c8721ac1
2020-11-11 12:01:03 +08:00
Algea Cao
aa2d780888 drm: rockchip: dw-hdmi: Add encoder mode set
Update hdmi phy ref clock in encoder mode set.

Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: I8e1df8e3d9e4109e9beae5bdaaf82ea8cc070407
2020-11-11 11:34:58 +08:00
Algea Cao
64d5fa4ad1 drm: rockchip: dw-hdmi: Set hdmi output interface to HDMI0
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ia9c694f73c1fe9ae3bdb4d8774658dca566ef6c2
2020-11-11 11:34:44 +08:00
Shunqing Chen
f8d70ba267 drm: rockchip: dw-hdmi: rename vpll_clk to accommodate more platforms
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Change-Id: I6d5aaacc241add2bbd20f2e16f2b4ae798e1db6a
2020-11-11 11:34:19 +08:00
Alex Zhao
209bad83d1 arm64: dts: rockchip: rk3566-evb1-ddr4-v10: fix for wifi/bt
Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Change-Id: I5beeb417f237e9cf306aa75743e02dc529690aa5
2020-11-11 11:28:04 +08:00
Guochun Huang
14586d46dd arm64: dts: rockchip: rk3568-evb: add dsi1
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I83b937aab46a9e4f28fb3540506dfb2305572e85
2020-11-11 11:21:57 +08:00
William Wu
62f5258931 phy: rockchip: naneng-combphy: fix mode set for usb3
This patch select pipe_txcompliance and pipe_l0_txelecidle
from usb3 controller for usb3 mode.

Change-Id: I6d354a974e431079e0f11fe84b75df583125818b
Signed-off-by: William Wu <william.wu@rock-chips.com>
2020-11-11 10:51:31 +08:00
William Wu
c90049e2ed arm64: dts: rockchip: rk3566-evb1-ddr4-v10: enable combphy1 for usb3 host
Change-Id: I6d76fe988714803fbab91d9a6ae4236b617dadae
Signed-off-by: William Wu <william.wu@rock-chips.com>
2020-11-11 10:51:31 +08:00
William Wu
762245fafd arm64: dts: rockchip: rk3568: set 24M ref clk for naneng combphy
Change-Id: Ie17a4bf16bd47e1e9fd6529873492ebcd11b5fae
Signed-off-by: William Wu <william.wu@rock-chips.com>
2020-11-11 10:51:30 +08:00
Zhenke Fan
847bb599e2 ARM: dts: rv1126-ai-cam.dtsi: modify link to cif by default
imx378 need to change the data lanes from <1 2> to <1 2 3 4>

Signed-off-by: Zhenke Fan <fanzy.fan@rock-chips.com>
Change-Id: Ifeb88250c7e01a4da84b67a0e77adcf0124201a9
2020-11-11 10:44:59 +08:00
Wyon Bi
09113e4c0a drm/rockchip: analogix_dp: Add member 'ssc' described in rockchip_dp_chip_data
Fixes: d7ad116fb3 ("drm/rockchip: analogix_dp: Add support for rk3568")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I42c4099e266ca8c97380c7c7021a967d7418dc88
2020-11-11 10:12:20 +08:00
Tao Huang
04f2db5f84 arm64: dts: rockchip: rk3568: Add reboot_mode label for Android
Support dtbo overlay reboot-mode for Android 10.

Fixes: f21a35d354 ("arm64: dts: rockchip: rk3568: add reboot-mode node")
Change-Id: If34ed638495374afd853ef46bbbc39b340e3de26
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2020-11-11 10:08:45 +08:00
Jon Lin
5252a54c3f arm64: dts: rockchip: rk3568-evb: Enable sfc node
Change-Id: I9551d00b000ddd20bf8c0814c2d19b045c0224b9
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
2020-11-11 10:08:07 +08:00
David Wu
20357c5158 arm64: dts: rockchip: rk356x: Change the rgmii delayline for rk3566-evb1
Change-Id: I95ce22b63785b5caf2abad5a4fd944b79ca51e33
Signed-off-by: David Wu <david.wu@rock-chips.com>
2020-11-11 09:36:47 +08:00
David Wu
8da4ac44d5 arm64: dts: rockchip: rk356x: Change the rgmii delayline for rk3566-evb2
Change-Id: I712621264fcbb4118429f509cd122912a2e82f7f
Signed-off-by: David Wu <david.wu@rock-chips.com>
2020-11-11 09:36:47 +08:00
David Wu
73552764da pinctrl: rockchip: use gmac1_rxd0 to select M0 and M1
It is better to select M0 and M1 iomux by gmac_rxd0, the
gmac_rxd0 would be used at RGMII and RMII.

Change-Id: I850dafcc8a9a826c25b9af7da3cf5b97208ea67f
Signed-off-by: David Wu <david.wu@rock-chips.com>
2020-11-11 09:30:39 +08:00
David Wu
8f4cd5a667 arm64: dts: rockchip: rk3568-pinctrl: Change the gmac tx pins drive strength to 15
Change-Id: Ie1eec34d7babf8aa9c8102167c4dcd43aa7d2b4e
Signed-off-by: David Wu <david.wu@rock-chips.com>
2020-11-11 09:28:58 +08:00
David Wu
73dc593e3d net: ethernet: stmmac: dwmac-rk: Add bus id to verify gmac0 and gmac1 for rk3568
Because there are two gmac controllers at rk3568, use
bus id to set the corresponding registers respectively.

Change-Id: Ie422e91075093bdcd2ed5ca11a7e3995aa75021a
Signed-off-by: David Wu <david.wu@rock-chips.com>
2020-11-11 09:28:05 +08:00
Andy Yan
0cab907042 drm/rockchip: vop2: Fix the setting of afbc stride
Change-Id: I0be42c042c5ce985fbd7d0d6216a5feb9794d7dd
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
2020-11-11 09:04:08 +08:00
Jianqun Xu
361820eab0 arm64: dts: rockchip: rk3568: fix io-domain node
Change-Id: I4d7d7aff6423ac31faf5d404e77a0f034d3b9bd1
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
2020-11-10 21:17:41 +08:00
Finley Xiao
1dafbf797b arm64: dts: rockchip: rk3568: Add clocks for pmu
Enable niu clocks before read qos.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ib3b39311cf105ca05f9a47a8739e591a4f311952
2020-11-10 20:42:17 +08:00
Finley Xiao
1ef89c8952 clk: rockchip: rk3568: Remove unused clk gate for gpu
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I219acca63d583bf6e4245709ef9d2fac858d6f2c
2020-11-10 20:40:32 +08:00
William Wu
a7f0b9fde1 phy: rockchip: inno-usb2: fix some issues for rk3568 usb2 phy
This patch fixes the following issues for rk3568 usb2 phy.

1. Only enable the id irq and bvalid irq for the port of combphy
   which used shared interrupt and work as otg/peripheral mode.

2. Enable the DP/DM pulldown resistors for the port of combphy
   if the port is used for usb host controller.

3. Set utmi opmode to no-driving for rk3568 usb phy when usb
   phy enter suspend mode via usb phy grf. It can help to
   avoid triggering the linestate irq constantly.

Change-Id: I3efe964c79865bef8ba70047f2ee20c59901ca6c
Signed-off-by: William Wu <william.wu@rock-chips.com>
2020-11-10 19:47:00 +08:00
William Wu
ce960453e1 arm64: dts: rockchip: rk3568: add usb2 phy nodes for usb host controllers
Change-Id: Id62fd95c0e016ab265ee248cb9a282241ab2d271
Signed-off-by: William Wu <william.wu@rock-chips.com>
2020-11-10 19:47:00 +08:00
Vitaly Chikunov
72b9859e0b UPSTREAM: perf arm64: Fix mksyscalltbl when system kernel headers are ahead of the kernel
When a host system has kernel headers that are newer than a compiling
kernel, mksyscalltbl fails with errors such as:

  <stdin>: In function 'main':
  <stdin>:271:44: error: '__NR_kexec_file_load' undeclared (first use in this function)
  <stdin>:271:44: note: each undeclared identifier is reported only once for each function it appears in
  <stdin>:272:46: error: '__NR_pidfd_send_signal' undeclared (first use in this function)
  <stdin>:273:43: error: '__NR_io_uring_setup' undeclared (first use in this function)
  <stdin>:274:43: error: '__NR_io_uring_enter' undeclared (first use in this function)
  <stdin>:275:46: error: '__NR_io_uring_register' undeclared (first use in this function)
  tools/perf/arch/arm64/entry/syscalls//mksyscalltbl: line 48: /tmp/create-table-xvUQdD: Permission denied

mksyscalltbl is compiled with default host includes, but run with
compiling kernel tree includes, causing some syscall numbers to being
undeclared.

Committer testing:

Before this patch, in my cross build environment, no build problems, but
these new syscalls were not in the syscalls.c generated from the
unistd.h file, which is a bug, this patch fixes it:

perfbuilder@6e20056ed532:/git/perf$ tail /tmp/build/perf/arch/arm64/include/generated/asm/syscalls.c
	[292] = "io_pgetevents",
	[293] = "rseq",
	[294] = "kexec_file_load",
	[424] = "pidfd_send_signal",
	[425] = "io_uring_setup",
	[426] = "io_uring_enter",
	[427] = "io_uring_register",
	[428] = "syscalls",
};
perfbuilder@6e20056ed532:/git/perf$ strings /tmp/build/perf/perf | egrep '^(io_uring_|pidfd_|kexec_file)'
kexec_file_load
pidfd_send_signal
io_uring_setup
io_uring_enter
io_uring_register
perfbuilder@6e20056ed532:/git/perf$
$

Well, there is that last "syscalls" thing, but that looks like some
other bug.

Signed-off-by: Vitaly Chikunov <vt@altlinux.org>
Tested-by: Arnaldo Carvalho de Melo <acme@redhat.com>
Tested-by: Michael Petlan <mpetlan@redhat.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Hendrik Brueckner <brueckner@linux.ibm.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kim Phillips <kim.phillips@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/r/20190521030203.1447-1-vt@altlinux.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
(cherry picked from commit f95d050cdc)
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Ie5381538e0bdf1dbb1bdff04b931487f6585328b
2020-11-10 19:33:08 +08:00
Xu Hongfei
489cae173f media: rockchip: vicap: support measuring luma in normal mode
Signed-off-by: Xu Hongfei <xuhf@rock-chips.com>
Change-Id: I5e36c03f46bd3362e288e3a3332caf412afe4a7b
2020-11-10 18:49:40 +08:00
Xu Hongfei
ce801a9bb6 media: rockchip: isp: set lgmean related regs for tmo in hdr isr
Signed-off-by: Xu Hongfei <xuhf@rock-chips.com>
Change-Id: I82cb63cff85e8b137a7b765601e57a8da0f99705
2020-11-10 18:49:40 +08:00
Sugar Zhang
358f15f02d pinctrl: rockchip: rk3568: Fix iomux for pdm
Change-Id: I44789839270af762ff8ea8b408740675f873f27d
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
2020-11-10 18:46:27 +08:00