Before reboot if the DCDC is disabled,
the DCDC is still disabled after restart.
We have an method to workaround:
Use vsel pin to switch the voltage between value in FAN53555_VSEL0
and FAN53555_VSEL1. If VSEL pin is inactive, the voltage of DCDC
are controlled by FAN53555_VSEL0, when we pull vsel pin to active,
they would be controlled by FAN53555_VSEL1.
In this case, we can set FAN53555_VSEL1 to disable dcdc,
So we can make vsel pin to active to disable dcdc,
VSEL pin is inactive to enable DCDC.
Change-Id: I14c823ed11dc3369044ad2ed0b53a6027acbccd0
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The pins from GPIO2B0 to GPIO2B6 are located at GRF_GPIO2BL_IOMUX,
they are recalculated to get correct iomux.
Change-Id: I1e46697c4508c396b5e8140c32c4185925a040ea
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The main description for rk3308b is as follows:
- Old iomux multiplexing extension;
- GRF_SOC_CON5 register add some bits;
- Newly added GRF_SOC_CON13/15 register.
Change-Id: I94bfcae5387aceae14895f1cafa0bfea51bf8b63
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
There are writable 32 bits for PMU_GPIO0's iomux, so add the
IOMUX_WRITABLE_32BIT to read iomux register at first, it would
not change others' bits.
Change-Id: I1fb27c60d5d26e5719b6911a78e7cdf144feba26
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The origin commit is 'pinctrl: rockchip: Add slew rate support for
px30', this commit only pick the support codes without px30, that will
be supported in another path.
The usage of slew rate is needed to config it at DTS,
such as:
fast speed: slew-rate = <1>;
slew speed: slew-rate = <0>;
Change-Id: Iefa9c15a35c6c1e94f716f5d6dd7e30d20a7293f
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
The gpio v2 has some new features:
- Use mask bit for register write;
- Both edge intterupt supported;
- longer debounce time for input intterupt.
Change-Id: I61f3974d2e0cf0e93c686aa11cd35162e59f393b
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
to slove the display shaking, when uboot logo display to kernel show.
Change-Id: I804aa09f24bc4fa7b6314a7a5487f0ee1a321724
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
others clk change it's parent from cpll to dummy_cpll.
the vop's parent just vpll and cpll,
make sure each vop have it's own pll as parent.
Change-Id: Ia61e10918e14a69c053455018ddf0183ff15ea19
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add cru and pmucru regs dump when system panic.
It's just for debug.
Change-Id: I3f837f2941054129d20c2355d86f575d6ee84665
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
These clock rate are used for HDMI display.
Change-Id: I4742dcfe8ddedfa6b86c38ce03bcaa5c28b34c4e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We need to declare that we enable all NOCs which are critical clocks
always and clearly and explicitly show that we have enabled them at
clk_summary.
Change-Id: I859664692b4d1bb0dda0ee38295dfcbc3cc70019
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
There are some clks(uart) that do not have to comply with the 20 times
fractional divider limit.
Change-Id: I420d8ba3b5de65d9e0ea74920d5ea8450ae94465
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add the clock tree definition for the new rk3568 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I9c2282938ec51ddf2dd71390b9b0cfef1f0d2735
This driver is modified to support RK3568 SoCs.
Change-Id: I5895cedad8c8e89f0657276c913e6e99d9544762
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This driver is modified to support RV1126 SoC.
Change-Id: I1a3c87d9b17b198e5cf5408b732b2a53363f4ef1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Some special applications of video may require:
rockchip_pmu_pd_on(dev)---> force power on pd
rockchip_pmu_pd_off(dev)---> force power down pd
rockchip_pmu_pd_is_on(dev)---> pd status
Change-Id: I264d76559aef0b0540130bf29a4635a3f5380a7c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
In order to fix deadlock between dmcfreq and vop on/off,
When change vop status and ddr frequency at the same time,
the following deadlock will happen:
vop no/off dmcfreq
vop_crtc_disable update_devfreq
->mutex_lock(&vop->vop_lock); ->mutex_lock(&pd->pmu->mutex);
->pm_runtime_put(vop->dev); ->mutex_lock(&vop->vop_lock);
->mutex_lock(&pd->pmu->mutex); ...
Change-Id: I56a4ee944200826d2a09e3ae8d2f4837f6f769d6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Use DOMAIN_RKXX_PROTECT to keepon the pd during startup.
Change-Id: I526b97ec273e056e703b6e187d0e6ffec44e730c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The power domains are supplied by regulators. Add support for them so
that the regulators are properly turned on before a domain is powered up
and turned off when a domain is powered down.
Change-Id: I43ad569e1b82a8e818cbbf2ffcfa6a965d993bbf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
It's not need to power on all pd when add pm domain.
Use pd's real status for pm_genpd_init().
Change-Id: I9a976f01c1b0ff192e09494dcfa236d786495e96
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This driver is modified to support RK1808 SoC.
Change-Id: Id622e126936a242f3dfbab94b0e7c7818b41f9ae
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We need to put the power status of HEVC IP into IDLE unless
we can't reset that IP or the SoC would crash down.
rockchip_pmu_idle_request(dev, true)---> enter idle
rockchip_pmu_idle_request(dev, false)---> exit idle
Change-Id: I76733efd2de4f7ee183c1b6bd1545d60038ee31b
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
