commit 4881873f4c upstream.
According to the public S805 datasheet the RESET2 register uses the
following bits for the PIC_DC, PSC and NAND reset lines:
- PIC_DC is at bit 3 (meaning: RESET_VD_RMEM + 3)
- PSC is at bit 4 (meaning: RESET_VD_RMEM + 4)
- NAND is at bit 5 (meaning: RESET_VD_RMEM + 4)
Update the reset IDs of these three reset lines so they don't conflict
with PIC_DC and map to the actual hardware reset lines.
Fixes: 79795e20a1 ("dt-bindings: reset: Add bindings for the Meson SoC Reset Controller")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
PD#SWPL-17563
Problem:
add power domain control API for TM2 and SM1
Solution:
add power domain control API for TM2 and SM1
Verify:
T962E2
Change-Id: I2587b2b554281ee7c81d77e8978a2640e5f73be5
Signed-off-by: zhiqiang liang <zhiqiang.liang@amlogic.com>
Signed-off-by: chunlong.cao <chunlong.cao@amlogic.com>
PD#OTT-5603
Problem:
Configurate GPIO_AO 9 as mclk_0,it doesn't work.
Solution:
From SM1, the mclk pad register is changed.
Using standard clk tree to make it compitable.
Verify:
TM2, SM1.
Change-Id: I8d53296297536c90768495232570f33fc89db131
Signed-off-by: Shuai Li <shuai.li@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
0504a9a audio: add clk tuning_enable/start_enable control in dts [1/1]
32dd894 audio: add lock for resampler [1/1]
2ad1050 audio: set hdmi format-check threshold by input samplerate [2/2]
953435d audio: fix TDMOUT channel map error [1/1]
9eace31 audio: auge: add lower power mode for PDM & vad [1/1]
90b9c44 audio: auge: add loopback driver [1/1]
0d736dd audio: add 10ms sleep before pdn enable [1/1]
51d1794 audio: add 10ms delay before pdn enable [1/1]
998f60b audio: disable tl1 acodec dac dapm to depop [1/1]
7b0ef35 audio: enable hw resmaple pause thd [1/1]
fcb2613 audio: TM2 bringup: enable ADC for linein [1/1]
4f4dc5a audio: TM2: bringup AMP ti5805 on ab301 [1/1]
758b24b audio: fixed kernel panic when resample is disabled [1/1]
19e844f audio: TM2 audio basic function bringup [1/1]
27c68d0 audio: add codec trigger mute for depop [1/1]
d415bb5 audio: fixed the issue of PDM 16 channel capture. [1/1]
d6e5cf5 audio: always on DDR arb [1/1]
0663274 audio: add HW resample for HDMIRX [1/1]
22f4718 audio: add param check for resample [1/1]
audio: add HW resample for HDMIRX [1/1]
PD#SWPL-6118
Problem:
No resample will cause mismatch between
input and output if they are not at same
samplerate.
Solution:
Add resample for hdmirx case
Verify:
Local tested.
Change-Id: I298e401578bf49484d6b75fd736d2a74c38508e4
Signed-off-by: Shuai Li <shuai.li@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
audio: always on DDR arb [1/1]
PD#TV-3452
Problem:
Toddr stuck after a long time playback.
Solution:
For debug usage.
Verify:
No need.
Change-Id: Ibf4446148f5e028040d7d6527c7695f23f964f7c
Signed-off-by: Shuai Li <shuai.li@amlogic.com>
Signed-off-by: Zhe Wang <Zhe.Wang@amlogic.com>
audio: fixed the issue of PDM 16 channel capture. [1/1]
PD#SWPL-5551
Problem:
cannot capture 8PDM + 8LOOPBACK.
Solution:
PDM cannot support 8PDM + 8LOOPBACK.
Verify:
s420/s400, verify pass
Change-Id: Iaf38bdcb218ebfc024666312162569cab93a76a9
Signed-off-by: Renjun Xu <renjun.xu@amlogic.com>
audio: add codec trigger mute for depop [1/1]
PD#SWPL-6944
Problem:
TV-3381
Speaker sometimes has clicking noise when playing DTV program.
Solution:
add codec trigger mute for depop
Verify:
Local verified.
Change-Id: Ib15a6b90bd3a6cdda2255afaf86daeab68ba07e2
Signed-off-by: Shuai Li <shuai.li@amlogic.com>
audio: TM2 audio basic function bringup [1/1]
PD#SWPL-6721
Problem:
TM2 bringup
Solution:
audio basic function bringup
Verify:
Verified on T962e2_ab311
Change-Id: Ic48ded3964ea87e40c4d683d71a50bbdc1975f91
Signed-off-by: Zhe Wang <Zhe.Wang@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
audio: fixed kernel panic when resample is disabled [1/1]
PD#SWPL-7039
Problem:
Kernel Panic when resample A is disabled
Solution:
When resample is disabled，don't init resample
Verify:
Verified on T962e2_ab311
Change-Id: Id9552ffc6be40f133b828dbded4ad3f15d177ab0
Signed-off-by: Zhe Wang <Zhe.Wang@amlogic.com>
audio: TM2: bringup AMP ti5805 on ab301 [1/1]
PD#SWPL-7074
Problem:
speaker doesn't work
Solution:
bringup AMP ti5805 on ab301
Verify:
Verified on T962x3_ab301
Change-Id: Icb27691b4fd5a1e54070c4a6d3d3c68cdf3a60b7
Signed-off-by: Zhe Wang <Zhe.Wang@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
audio: TM2 bringup: enable ADC for linein [1/1]
PD#SWPL-7027
Problem:
audio path AVin is on audio
Solution:
enable ADC for linein
Verify:
Verify on AB311
Change-Id: Iea1d694e0b605d62596635d85416d33f56dbbcb2
Signed-off-by: Zhe Wang <Zhe.Wang@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
audio: enable hw resmaple pause thd [1/1]
PD#TV-4638
Problem:
Speaker output high frequency howling
after change from pattern 615 to pattern 1 on chroma22294.
The hw resampler keeps sending noise if it has no input.
Solution:
Enable the hw resample pause thd by default.
Verify:
TL1 X301.
Change-Id: Ib6f0924025e155eaa8ba0e3681b307f7ff56b449
Signed-off-by: Shuai Li <shuai.li@amlogic.com>
audio: disable tl1 acodec dac dapm to depop [1/1]
PD#TV-3933
Problem:
Tl1 acodec has pop sound when first sound appear.
Solution:
Disable the DAPM which disable/enable every time
start/stop the audio stream.
Verify:
Tl1 X301.
Change-Id: Iaaf7da125de513bd8297f6c6e41af0a42c9d25bd
Signed-off-by: Shuai Li <shuai.li@amlogic.com>
audio: add 10ms delay before pdn enable [1/1]
PD#SWPL-7680
Problem:
the pwn signal is self excitable
Solution:
1)add 10ms delay before pdn enable
2)set default clk for extern codec
Verify:
HW verify
Change-Id: I031b20851ee1eeb65215075fc8abe783ceddf42b
Signed-off-by: Zhe Wang <Zhe.Wang@amlogic.com>
audio: add 10ms sleep before pdn enable [1/1]
PD#SWPL-7680
Problem:
mdelay will pend the system
Solution:
change mdelay to usleep_range
Verify:
HW verify
Change-Id: I8452dc7b1056378dbc6b743fc43316eccbf525a5
Signed-off-by: Zhe Wang <Zhe.Wang@amlogic.com>
audio: auge: add loopback driver [1/1]
PD#SWPL-7240
Problem:
limit of current loopback
add loopback b for tl1
add tdmin_lb
Solution:
optimize loopback driver
Verify:
s400, u200, x301, ac200, ab301
Change-Id: I9dd4c7ad041231bb2c49513e354cfb4fb92131c4
Signed-off-by: Xing Wang <xing.wang@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
audio: auge: add lower power mode for PDM & vad [1/1]
PD#SWPL-3825
Problem:
VAD & PDM works in 24m clks for lowpower mode when in deep suspend
Solution:
support VAD & PDM in 24m sysclk, 768k dclk
Verify:
x301
Change-Id: Ic363337ee9b0eba0f890ae62b9e0cb6bb54dcd6a
Signed-off-by: Xing Wang <xing.wang@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
audio: fix TDMOUT channel map error [1/1]
PD#SWPL-6427
Problem:
ALSA tdmout buffer frequently underrun.
This will cause the tdmout channel map error.
And the other channels data go into the spk.
Solution:
1)Adjust the sequence of starting and stopping.
2)reserved frddrA for EQ/DRC module
Verify:
Test more that 1 hour and pass.
Need more stress test.
Change-Id: Ib9b6897f0b6c32652c611a8c2c367aa76b9f1e3f
Signed-off-by: Shuai Li <shuai.li@amlogic.com>
Signed-off-by: Zhe Wang <Zhe.Wang@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
audio: set hdmi format-check threshold by input samplerate [2/2]
PD#SWPL-6340
Problem:
ddp audio input from hdmiin is not smooth
Solution:
set hdmiin format-check threshold by input sr
Verify:
Verified by x301.
Change-Id: Idb8ffa616c3880b1c34d61ca4e8c2917343a9ffc
Signed-off-by: Zhe Wang <Zhe.Wang@amlogic.com>
audio: add lock for resampler [1/1]
PD#SWPL-8134
Problem:
kernel NULL pointer for aml_resample_enable
Solution:
add lock for resampler
Verify:
Need stress test for x301
Change-Id: I1bbf5d7aeab681399c93f0cba9cc59195d3be0d6
Signed-off-by: Shuai Li <shuai.li@amlogic.com>
audio: add clk tuning_enable/start_enable control in dts [1/1]
PD#SWPL-8306
Problem:
speaker without audio on S400. sideeffect of SWPL-7680
Solution:
add control interface in dts to enable clk tuning
and start clk before codec init
Verify:
verify on S400
Change-Id: Ic9f4e7b13b7d4ced18852346cdc7cf5f48e510dc
Signed-off-by: Zhe Wang <Zhe.Wang@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
audio: add param check for resample [1/1]
PD#SWPL-7798
Problem:
Crashed when audio resample setting params
are invalid.
Solution:
Add check method if the params is invalid.
Verify:
Tl1.
Change-Id: I1e0396be8d401c0a49ff0de9fd7f160f0c8133ca
Signed-off-by: Shuai Li <shuai.li@amlogic.com>
Signed-off-by: Luan Yuan <luan.yuan@amlogic.com>
PD#SWPL-5407
Problem:
not include sm1 special defined clk
Solution:
add this clk
Verify:
sm1_skt
Change-Id: Iaf20aebe377d077d95eb053f7eea99473e3ac45d
Signed-off-by: Shunzhou Jiang <shunzhou.jiang@amlogic.com>
PD#SWPL-3359
Problem:
the bt656 clocks were missing
Solution:
1.add bt656 clocks
2.fix several errors for media clocks
Verify:
test passed on u200
Change-Id: Iff69e790c78335930d6b2ea54f7544aca464e1fb
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#OTT-1025
Problem:
not support gen clock
Solution:
add gen clock
Verify:
test passed on g12a u200
Change-Id: I5199289d3cd1483fffbbd41f8d104369214ba302
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#172587: arm: dts: tl1: add initial device tree for tl1
Change-Id: I17734ee00d88a84ff19bf17f8edf519e3ed2f0e4
Signed-off-by: Bo Yang <bo.yang@amlogic.com>
PD#168480: pinctrl: txl: add pinctrl & gpio support for txl
Change-Id: I2496cdebfc283e90825f5dd7d20b0e16f57158d2
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
Signed-off-by: Bo Yang <bo.yang@amlogic.com>
PD#168480: clk: txl: initial add clock driver
remove CLK_SET_RATE_PARENT flag for spicc.
If add CLK_SET_RATE_PARENT, it will change clk81 rate when set
spicc clock rate.
Change-Id: I80fec2c6d10611994ff40b06307e39b51ddb5a1a
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
Signed-off-by: Bo Yang <bo.yang@amlogic.com>
PD#165090: add g12b.c for new clocks, include sys1_pll
Change-Id: If9234037eab5439cf1abfbcecc70c9f4eab6c954
Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
Signed-off-by: Hong Guo <hong.guo@amlogic.com>
Signed-off-by: Victor Wan <victor.wan@amlogic.com>
Conflicts:
arch/arm/configs/bcm2835_defconfig
arch/arm/configs/sunxi_defconfig
include/linux/cpufreq.h
init/main.c
PD#163124: pinctrl: keep the same GPIO ID after adding GPIOV_0 for G12A
Change-Id: I45b99df3a15e2bf0f7ad34ae8705dc4a509c70a1
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
PD#162992: pinctrl: add virtual GPIO "GPIOV_0" for g12a
The gpio is used to set the bit PERIPHS_PIN_MUX_2 BIT[17]. Please refer
the following method to use it.
1). set the PERIPHS_PIN_MUX_2 BIT[17] to <1>
mux_en {
groups = "sdio_dummy";
function = "sdio";
}
2). set the PERIPHS_PIN_MUX_2 BIT[17] to <0>
mux_dis {
groups = "GPIOV_0";
function = "gpio_periphs";
}
Change-Id: Ied0e6c71ed1ff8ab9a26cb76ec1508d83a4453d7
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
PD#161621: gpio: core: Decouple open drain/source flag with active low/high
Currently, the GPIO interface is said to Open Drain if it is Single
Ended and active LOW. Similarly, it is said as Open Source if it is
Single Ended and active HIGH.
The active HIGH/LOW is used in the interface for setting the pin
state to HIGH or LOW when enabling/disabling the interface.
In Open Drain interface, pin is set to HIGH by putting pin in
high impedance and LOW by driving to the LOW.
In Open Source interface, pin is set to HIGH by driving pin to
HIGH and set to LOW by putting pin in high impedance.
With above, the Open Drain/Source is unrelated to the active LOW/HIGH
in interface. There is interface where the enable/disable of interface
is ether active LOW or HIGH but it is Open Drain type.
Hence decouple the Open Drain with Single Ended + Active LOW and
Open Source with Single Ended + Active HIGH.
Adding different flag for the Open Drain/Open Source which is valid
only when Single ended flag is enabled.
Note: the patch from v4.14-rc6 with original commit ID 4c0facddb
Change-Id: I2f652614d3783caee3f510dc70e5e185379f49a7
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
PD#158433: arm64: dts: add i2c alias in aliases node
add alias for i2c controller to fasten i2c dev id
Change-Id: I87c1999766c69e9df63f551f0559b8028844d660
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#156734: pinctrl: add pinctrl&gpio support for g12a
the new pin feature (drive-strength) is first introduced in Meson
Series SoC [G12A]. we can refer the following example to use:
mux {
groups = "uart_ao_tx_a", "uart_ao_rx_a";
function = "uart_ao_a";
drive-strength = <1>;
}
the value of drive-strength can be set to 0/1/2/3, the larger
the value, the faster the slew rate.
Change-Id: I22c6967aa1d5de1b3f6acb84cb18a79b05c0403b
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
PD#156734: base clock tree for G12A,
include clk81, ee gate, sdemmc clock, fix/hifi/syspll/pcie plls, mpll, clkmsr
Change-Id: I9fe7c1d64d9db5d384070f5dcefdc69f5f60dbd2
Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
PD#157965: pinctrl: define the pinmux with the same format.
there are two different pin controllers in Meson Soc Series, one of
them uses continuous 4-bit register to select function for each pin
(Eg: AXG and next), the other use indefinite bits that maybe from
different registers (Eg: Before AXG and GXLX)
previously, the driver use two different format to define the pinmux,
as follows:
[1] Before AXG and GXLX:
mux {
groups = "uart_ao_tx_a", "uart_ao_rx_a";
function = "uart_ao_a";
}
[2] AXG and next
mux {
pins = "GPIOAO_0", "GPIOAO_1";
function = "uart_ao_a";
}
which is a little confusing，and in this patch define the pinmux with
one format[1].
Change-Id: I04fb256294e1b664224c50a1baa622eb3a50b1c1
Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
PD#154260: clk: meson-txlx: add clock tree driver
Change clkc driver init order
The loading order of vpu driver is postcore_initcall,
but clock order is device_initcall.clock order should
be higher,change macro CLK_OF_DECLARE instead
Optimizing mux/div/gate descriptions.
Change-Id: I20cd8111ac6bd60f350cdddc224bad48c13fcfb1
Signed-off-by: Jian Hu <jian.hu@amlogic.com>
PD#152261: clk: update clk total number
add bt656 clk, but total number not update
Change-Id: I24f2f17e4e773a883bab3f564144a49768fc16d5
Signed-off-by: wenbiao zhang <wenbiao.zhang@amlogic.com>
[ Upstream commit d97556c801 ]
We need to also have OFFPULLUDENABLE bit set to use the off mode pull values.
Otherwise the line is pulled down internally if no external pull exists.
This is has some documentation at:
http://processors.wiki.ti.com/index.php/Optimizing_OMAP35x_and_AM/DM37x_OFF_mode_PAD_configuration
Note that the value is still glitchy during off mode transitions as documented
in spz319f.pdf "Advisory 1.45". It's best to use external pulls instead of
relying on the internal ones for off mode and even then anything pulled up
will get driven down momentarily on off mode restore for GPIO banks other
than bank1.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
[ Upstream commit 5ccb58968b ]
Add missing identifiers for phyclk_mipidphy0_bitclkdiv8_phy and
phyclk_mipidphy0_rxclkesc0_phy clocks. Access to those clocks is needed
to setup initial clock configuration for display subsystem in device tree
in order to avoid dependency on the configuration left by the bootloader.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
PD#146437: axg: add mipi enable and bandgap gate and
update clkmsr for cts_encl_clk
Change-Id: If14ede7ab0a0b649879153cb1089bec04c7412b2
Signed-off-by: Yun Cai <yun.cai@amlogic.com>
