others clk change it's parent from cpll to dummy_cpll.
the vop's parent just vpll and cpll,
make sure each vop have it's own pll as parent.
Change-Id: Ia61e10918e14a69c053455018ddf0183ff15ea19
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add cru and pmucru regs dump when system panic.
It's just for debug.
Change-Id: I3f837f2941054129d20c2355d86f575d6ee84665
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
These clock rate are used for HDMI display.
Change-Id: I4742dcfe8ddedfa6b86c38ce03bcaa5c28b34c4e
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We need to declare that we enable all NOCs which are critical clocks
always and clearly and explicitly show that we have enabled them at
clk_summary.
Change-Id: I859664692b4d1bb0dda0ee38295dfcbc3cc70019
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
There are some clks(uart) that do not have to comply with the 20 times
fractional divider limit.
Change-Id: I420d8ba3b5de65d9e0ea74920d5ea8450ae94465
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add the clock tree definition for the new rk3568 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I9c2282938ec51ddf2dd71390b9b0cfef1f0d2735
This driver is modified to support RK3568 SoCs.
Change-Id: I5895cedad8c8e89f0657276c913e6e99d9544762
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This driver is modified to support RV1126 SoC.
Change-Id: I1a3c87d9b17b198e5cf5408b732b2a53363f4ef1
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Some special applications of video may require:
rockchip_pmu_pd_on(dev)---> force power on pd
rockchip_pmu_pd_off(dev)---> force power down pd
rockchip_pmu_pd_is_on(dev)---> pd status
Change-Id: I264d76559aef0b0540130bf29a4635a3f5380a7c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
In order to fix deadlock between dmcfreq and vop on/off,
When change vop status and ddr frequency at the same time,
the following deadlock will happen:
vop no/off dmcfreq
vop_crtc_disable update_devfreq
->mutex_lock(&vop->vop_lock); ->mutex_lock(&pd->pmu->mutex);
->pm_runtime_put(vop->dev); ->mutex_lock(&vop->vop_lock);
->mutex_lock(&pd->pmu->mutex); ...
Change-Id: I56a4ee944200826d2a09e3ae8d2f4837f6f769d6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Use DOMAIN_RKXX_PROTECT to keepon the pd during startup.
Change-Id: I526b97ec273e056e703b6e187d0e6ffec44e730c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The power domains are supplied by regulators. Add support for them so
that the regulators are properly turned on before a domain is powered up
and turned off when a domain is powered down.
Change-Id: I43ad569e1b82a8e818cbbf2ffcfa6a965d993bbf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
It's not need to power on all pd when add pm domain.
Use pd's real status for pm_genpd_init().
Change-Id: I9a976f01c1b0ff192e09494dcfa236d786495e96
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This driver is modified to support RK1808 SoC.
Change-Id: Id622e126936a242f3dfbab94b0e7c7818b41f9ae
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We need to put the power status of HEVC IP into IDLE unless
we can't reset that IP or the SoC would crash down.
rockchip_pmu_idle_request(dev, true)---> enter idle
rockchip_pmu_idle_request(dev, false)---> exit idle
Change-Id: I76733efd2de4f7ee183c1b6bd1545d60038ee31b
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
There is a lower power dissipation requirement for some products, like
battery ipc, bell, etc... We have to gate cpll/hpll to reduce power
dissipation.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I48fae621c980b6f7f7d8e8ca71171febd6c6a9a8
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
set pll sequence:
->set pll to slow mode or other plls
->set pll down
->set pll params
->set pll up
->wait pll lock status
->set pll to normal mode
To slove the system error:
rockchip_rk3399_wait_pll_lock: timeout waiting for pll to lock
rockchip_rk3399_pll_set_params: pll update unsucessful,
trying to restore old params
Change-Id: I62aecd9f292de5a3c7bcd8a87231785bf115159d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
If setting freq is not support in rockchip_pll_rate_table rk3399_pll_rates[],
It can set pll params by auto.
Change-Id: I5016cece64dca4c2efec18d552ee6be426f6b95a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add cru regs dump when system panic.
It's just for debug.
Change-Id: I3aeeeb7f7b9240c917c18bc2d36b082003dc6370
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Rockchip socs often have some tiny number of muxes not controlled from
the core clock controller but through bits set in the pmugrf.
Use MUXPMUGRF() to cover this special clock-type.
Change-Id: Iac962a27a3c88ce188d03c416cb4b3b45a462c0a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
There is a new clock branch have a form like
|--\
Change-Id: I6a7c17cb782b13965f537f44c103611e00d1ecad
---[GPLL]---| \ |--\
---[CPLL]---|mux|-----[GATE]--[DVI]------| \
---[HPLL]---| / | |mux|--[GATE]--
|--/ |--[GATE]--[HALFDVI]--| /
|--/
This patch registers two composite clocks for this branch type,
and make them become brother clock for each oher.
Change-Id: I46aeab26e478f341600114014db1c7d58e234f11
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Some composite clocks may have the same parent clock, if one clock change
the parent clock rate, the other clock rate may too large, so add a
brother clock in composite that the other clock also can be changed when
parent rate is changed.
Change-Id: I2c6749e578b76d6780cecdcd9ff1b5fd4f25a0ba
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The CLK_SET_RATE_PARENT flag make the parent clock and the child clk is 1:1.
If the DCLK frequency is too low, the PLL frequency will be very
low, which will affect the output waveform quality of PLL, and PLL
locking may be abnormal, so add a new COMPOSITE_DCLK clock-type to handle
that.
Change-Id: If9bee9ebf157fcf034aed246b3aa1cff503ef9cf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
We know that under the condition of even frequency division,
if the numeratoris greater than 4, the duty cycle may not be
equal to 50%.
In the case, weneed to keep the original numerator(<4) and
denominator.
Change-Id: I8cd08199df4e3d27d5697ce80370224a6f267e26
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
From Rockchips fractional divider usage, some clocks can be generated
by fractional divider, but the input clock frequency of fractional
divider should be less than a specified value.
Change-Id: Ifd6c5f6a24a64021f990506e8657cd925f9b96f9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
