for vp2/vp3, we can use hardware or software TE to sync with panel ram,
but for vp1->dsc1->dsc1 path, we only can use software TE to sync with panel
ram.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I0f54723c5c1c45916e669ce21819a127dc5b415d
gc032a & ov2680 for rk3368a tablet
gc2355 for rk3399 tablet
this tablets not exist now
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: I95e2d20fbbe6b61ecbc2117a3ea67e801e8892f4
DLL will not LOCK after frequency reduction, DLL will not LOCK after
frequency reduction,
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I2176ff4b003e33efec049209083fe3a4d38fc10c
RK3588S-EVB1 only have two display(VP1 for DP and VP2 for eDP),
so we can assign 8 windows by 4+4.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: Ibec566e2bf4497c8aca2e732ff43b2a293127bd3
1. Modify the definition of version number.
2. Add to get the driver version interface.
3. Add to get the hardware version interface.
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Ia8d8bcb476adc6af5a64a009f0e5cade93e083ac
This patch aims to configure sata for better compatibility.
1. Set ssc downward spread spectrum.
2. Enable the adaptive Continuous Time Linear Equalizer (CTLE).
3. Set ssc to 31.5KHz for 24MHz ref clk.
4. Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: Iec71d588183bf89a65d6cbce7635dd8768f2ea5d
enable the lt7911d DP/type-c to MIPI-CSI2 bridge driver used for
rk3588s-evb ExtBoard
Signed-off-by: Jianwei Fan <jianwei.fan@rock-chips.com>
Change-Id: I1a48f1f4c375e1d32992ba104fd6a5619486b08c
TRNG_V1_STAT_GENERATING is generated abnormally, but the
corresponding TRNG_V1_ISTAT_RAND_RDY flag cannot be triggered
in sometimes.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: I446b8d521075057d07f842041f790075aec402a1
combophy relies on rockchip,pcie1ln-sel-bits to specify
lane mux for each devices. During system PM, genpd will
be turned off, so lane mux information will lost. So we'd
better move it to rockchip_combphy_pcie_init() as it will
be called both for probing and resuming.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I69a0754d7f67a95d97bde71ef629135a59a2c64b
only disable capture_en may cause memory access error
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Change-Id: Ia3c7e5a07b3d95c762735e1b73170fb1911f48da
make ARCH=arm64 rockchip_linux_defconfig rk3588_nvr.config
Signed-off-by: Mark Huang <huangjc@rock-chips.com>
Change-Id: I94f8a89aff5795817690b8d6b8796f9cb9c0b70a
Fixes: ca885383eb ("drm/rockchip: dw-dp: support dynamic binding to different vp port")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I94654e6eb916d688d9fe46544f60bd02e8d8cb7b
ACR located at Packet Scheduler which belongs to VIDQPCLK domain.
So, the related clk should be enabled before register access.
Actually, There are three CLK domain (AUDCLK, VIDQPCLK, LINKQPCLK)
related to Audio. So, do check clk status before config audio.
Maybe the better way should be spliting hdmi regmap into several parts
which managed by related clk domain in future.
e.g.
devm_regmap_init_mmio_clk(dev, "aud", regs, AUD_REGBANK);
devm_regmap_init_mmio_clk(dev, "vidqp", regs, VIDQP_REGBANK);
devm_regmap_init_mmio_clk(dev, "linkqp", regs, LINKQP_REGBANK);
...
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ib497d92a73d99d9f38c4617f615f02c705b82ae7
We move all the probe stuff to kthread so that it won't block
the system to go on probing other drivers. But that introduced
a bug that PM calls would not be removed by driver core. As each
platform driver uses the same PM callbacks for all device instances.
So add device_release_driver if it fails to probe devices.
Fixes: 79ac46bdea ("PCI: rockchip: dw: Add kthread to probe PCIe devices")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I9d6ba448a87defa8d924927f1bfcff51c889e1a0
When phy status is none, it mean that the power off
process is already be run. if the phy power off
function is called again before power on, ignore it.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I34c3f2b92076f7c27a1537d3c78000781de61179
when we set mode change flag and the phy is idle, here
will not clear the mode change flag when power on, we
need clear it.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I900d5c37a2e83212eb6461d714a653c93da923c7
