The bigger the divider, the better the clock jitter.
Change-Id: I4b4e06c71c2f0bdb0e32422fb42c8d490c3ec4bd
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Zero is a valid value for half-divider.
Change-Id: I23aa8afcd391da95396e5d808c3c424f993c66e3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The div offset of some clocks are different from their mux offset
and the COMPOSITE clock-type require that div and mux offset are
the same, so add a new COMPOSITE_DIV_OFFSET clock-type to handle that.
Change-Id: I7d541e29328f37d2ad806b3b6e5ab35b5513b345
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
support fractional divider with only one level parent clock
Change-Id: I6593f908edf4454ef03255080bf9ac1d72c6f64e
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
crypto and dmac share the same noc clk,
so mark the aclk_dmac1 as critical clk.
Change-Id: I34a4a7cc532a385086679fafb961a47b0a6abc3b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
crypto and dmac share the same noc clk,
so mark the aclk_dmac_bus as critical clk.
Change-Id: Ib0b70bbed3fdefeab7b6f2b5f88350a416e66787
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The serial Flash controller on the rk3036 would request
two clock nodes.
Change-Id: Iaa50c4a25602a68241b0b9b2f186e4c7e55bc3da
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The power domains are supplied by regulators. Add support for them so
that the regulators are properly turned on before a domain is powered up
and turned off when a domain is powered down.
Change-Id: I43ad569e1b82a8e818cbbf2ffcfa6a965d993bbf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
It's not need to power on all pd when add pm domain.
Use pd's real status for pm_genpd_init().
Change-Id: I9a976f01c1b0ff192e09494dcfa236d786495e96
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This driver is modified to support RK1808 SoC.
Change-Id: Id622e126936a242f3dfbab94b0e7c7818b41f9ae
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This patch set attempts to new compatible for thermal founding
on RK1808 SoCs.
Change-Id: I133218cd958e0aabf711a5d22fe5e5da2fbd59ce
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Based on the TSADC Tshut mode to select pinctrl,
instead of setting pinctrl based on architecture
(Not depends on pinctrl setting by "init" or "default").
And it requires setting the tshut polarity before select pinctrl.
Change-Id: Ieb181ec19dedbbfb7aef474b3558aac867e668eb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
init temp_last with a more suitable value. also we eliminate
the steady state error by ajusting the temp calc fomular.
extra useful log is added to mark tsadc is probed successfully.
Change-Id: If88031c10646437fa7b5152c70aeaebf93e4df05
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
the mux_spdif_8ch_p is composed of spdif_8ch_src not spdif_8ch_pre
Change-Id: I7dd40e35078b2d012af2c777de763d14e93c3d4e
Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
From Rockchips fractional divider usage, some clocks can be generated
by fractional divider, but the input clock frequency of fractional
divider should be less than a specified value.
Change-Id: Ifd6c5f6a24a64021f990506e8657cd925f9b96f9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
If change parent to alternate parent and the old parent clock speed is less
than the clock speed of the alternate parent, add dividers first and then
select alternate parent.
If change parent to primary parent, select primary parent first and then
remove dividers.
Change-Id: Ib82de9a936effe5c885639799f3bb5629dc89f8d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Tsadc has a tshut pin which is designed to reset the pmic or soc,
when the temperature inside soc is too high. we should switch off
the tshut function and change the pin to gpio function in reboot
process, eg, software reset. If not, the tsadc module will WRONGLY
pull high the tshut pin during its reset process and then WRONGLY
reset the pmic or soc, which incurred a hardware reset. The hardware
reset will reset everything inside soc, even includes the power on
reason flag, which is set by software before reboot process.
we also change over-temperature protection mode to cru mode,
since the tshut pin have be changed to gpio function.
Change-Id: Iac3dacf55a4b5536fccd2eb05a6a9e6923a082c0
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Prevent the system from entering suspend when usb cable is connecetd.
Change-Id: I50c4a09d9142ebeb2d4e2a0ab2df59f98ef99737
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch adds bypass uart cfgs for rk1808 USB 3.0 OTG
port. In addition, please note that it needs to set the
uart2 rx/tx io selection in the reg "BUS_GRF_IOFUNC_CON0"
bit 15:14.
Change-Id: I77ea461be299c0454f5caee1349110b6f2714c30
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
RK1808 SoC has an usb 2.0 comb phy with one otg-port and one
host-port. This patch adds port configurations for them.
Change-Id: Id4d117929ec0e327c8f2cc1a06d4caaa2d584f06
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
We find an usb phy 480MHz clk prepare fail issue on PX30/RK3326
platforms with RK819 PMIC. On PX30/RK3326 platforms, we set the
usb480m clk to critical because GPU 480M is from usb480m and the
source clocks should be always on. And the usb phy 480MHz clk is
parent of usb480m clk, so the clk framework will prepare the usb
phy 480MHz clk when register it.
This logic works well if the usb phy probe only once. But if the
usb phy needs to probe twice or more because of some reasons (e.g.
fail to get vbus regulator from RK819), the usb phy 480MHz clk will
be unregistered and registered again, however, the clk framework
doesn't prepare the usb phy 480MHz clk except the first time register
operation. So we move the 480MHz clk register to the end of probe,
and make sure only register it once.
Change-Id: If69378b49035746a7c0107c6a363c4d91dfc15e5
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
