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Author SHA1 Message Date
Andy Yan
5df67251b8 drm/rockchip: vop2: Rewrite vsc_gt2/gt4 check logic 
Use multiplication instead of division.
when gt4 enabled: src_h >>= 2;
when gt2 enable: src_h >>=1;

Change-Id: If47f873668f61b9a0690c665079bddfacc8429b5
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2020-11-18 21:32:31 +08:00
Ziyuan Xu
4f43c95883 soc: rockchip: sdmmc_vendor_storage: reduce wait as far as possible 
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I69d409e132b1bf11377e38b0e093389a7059cd6f
 2020-11-18 20:10:12 +08:00
Andy Yan
1221fbb694 drm/rockchip: vop2: Add vsd_yrgb_gt2/gt4 register definition for cluster 
Change-Id: I80b928191754cdb2c7d4ad2157b77bdbdcb955ad
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2020-11-18 19:54:14 +08:00
Andy Yan
18b66b881f drm/rockchip: vop2: Add color components swap 
Change-Id: I124f92fadc2494311b950657bbb0176d65aff08b
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2020-11-18 19:54:14 +08:00
Huang zhibao
abc2dfbb6e arm64: rockchip_linux_defconfig: enable CONFIG_PHY_ROCKCHIP_NANENG_EDP 
Enable the eDP PHY driver used on Rockchip RK3568 SoC.

Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: Id6480ae7eb9fd82ec35fbde60b59e6a1e1483d5e
 2020-11-18 19:46:14 +08:00
Yu Qiaowei
d1ce375ca1 video/rockchip: rga2: Fix errors in Y4/Y400 format. 
1. Modify the calculation of Y400/Y4 buffer size.
2. Add print of result and pageCount.
3. Add Y4/Y400 string name.

Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Change-Id: Ibe26b7b900c317d28e0c4326f0c89a244a0017b0
 2020-11-18 19:45:21 +08:00
Wyon Bi
cbee98b758 drm/bridge: analogix_dp: Add NULL pointer check for dp->phy 
Fixes: d7ad116fb3 ("drm/rockchip: analogix_dp: Add support for rk3568")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I8cef87e13dd7c03baac730523c8f4b98d1a043f2
 2020-11-18 19:43:52 +08:00
David Wu
66d48911ac arm64: dts: rockchip: Change the gmac1m0 rgmii delayline for rk3568-evb6 
Change-Id: I65d6122bd0a3cc5976333c844ed6fad61e0e6627
Signed-off-by: David Wu <david.wu@rock-chips.com>
 2020-11-18 17:57:56 +08:00
Yao Xiao
ac460ece42 net: rockchip_wlan: rtl8188fu: update to v5.7.4.2_36687.20200814 
Signed-off-by: Yao Xiao <xiaoyao@rock-chips.com>
Change-Id: Ief53844ec96dd572d5822c028cf472a12b35f173
 2020-11-18 17:52:06 +08:00
Simon Xue
ce845b03c2 iio: adc: rockchip_saradc: add support for RK3568 
Change-Id: I9d83351b1117eba67277cdd0a32e5d0c59ad1c7f
Signed-off-by: Simon Xue <xxm@rock-chips.com>
 2020-11-18 17:43:32 +08:00
Guochun Huang
09f5dd4822 drm/rockchip: dsi: make timing and lane rate more accurate 
use actual pixel or dot clock in the hardware to calc the
timings and lane rate if dclk can not be applied accurately.

Change-Id: I6c0bcaca35cb945a58cc50005b23c6c772c9a082
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
 2020-11-18 17:09:05 +08:00
Elaine Zhang
afba90dde0 arm64: dts: rockchip: rk3568: support clk_32k_ioe output 32k 
add xin32k dts node.
assigned-clock-parents for clk_32k_ioe.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I63500026e32b4dfe5debe3a2aa79f111e42a5fbc
 2020-11-18 16:56:47 +08:00
Simon Xue
0cd2eda71e PCI: rockchip: update udma trx logic 
Move udma related config and start operation to master place and expose
as a hook, udma trx obj just call the hook.

Change-Id: If410280629eafa9d8829ac89a8cef6e931b37c3c
Signed-off-by: Simon Xue <xxm@rock-chips.com>
 2020-11-18 16:49:50 +08:00
Wu Liangqing
fd5622d13c arm64: dts: rockchip: rk3566-evb3: bringup 
Change-Id: I3717b8efd22e70f4d661f2c0828320760876beb0
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
 2020-11-18 16:17:36 +08:00
Liang Chen
2f153f1fa7 arm64: dts: rockchip: rk3568: add thermal-zone for pvtm 
Change-Id: Ie082e512265e3e416582a03ad4b1efe97dc5f98e
Signed-off-by: Liang Chen <cl@rock-chips.com>
 2020-11-18 15:41:47 +08:00
Ding Wei
06a91e1527 arm64: dts: rockchip: rk3568: set codec relative clock freq 
Change-Id: Icd3de01aeb6887add17966aa02515623a933e7ee
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
 2020-11-18 15:41:13 +08:00
Hans Yang
d4cec57949 arm64: rockchip_linux_defconfig: enable mpp relative codec 
CONFIG_MPP_ROCKCHIP_RKVDEC2: rkv-decoder-v2
CONFIG_MPP_ROCKCHIP_RKVENC:  rkv-encoder-v1
CONFIG_MPP_ROCKCHIP_JPGDEC:  rkv-jpeg-decoder-v1

Signed-off-by: Hans Yang <yhx@rock-chips.com>
Change-Id: I18a8a36ddc460870c6bbde8cd85579a32c4b0a64
 2020-11-18 15:32:08 +08:00
Andy Yan
8349065753 drm/rockchip: vop2: Fix format definition 
Change-Id: I8197ed19f3829858006205b995068458119a8c28
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2020-11-18 15:30:09 +08:00
Elaine Zhang
c4dba0f561 clk: rockchip: rk3568: fix up the mac clk definition error 
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I058a1f3997aca13c25bad769a492b91a0c5fd2f5
 2020-11-18 15:25:29 +08:00
Elaine Zhang
e13a0ea1af clk: rockchip: rk3568: export SCLK_32K_IOE clock id 
Add clk_32k_ioe to select 32k io as input or output.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I8347b34b43244b1dca0217d9af56fcf9c414d18e
 2020-11-18 15:18:26 +08:00
Jianqun Xu
ca3705f1ab arm64: dts: rockchip: rk3568-iotest-ddr3-linux support 
Change-Id: Ib1e91da34f29b1e823f0715294fc6230fa9d7da9
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2020-11-18 11:44:27 +08:00
Andy Yan
0f14c0d4e8 drm/rockchip: vop2: Count afbc vir stride by pixel 
Change-Id: Ie153a014f059238cba5752d323beecf04b1d47b9
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2020-11-18 11:40:57 +08:00
Andy Yan
9d17e9ed6a drm/rockchip: vop2: Disable afbc auto gating 
Some resolution(eg: 4096x2049) can't display when AFBC auto gating
enabled.

Change-Id: Iadd2db1e600c7c0bae10ead0851476f2cf3bbe34
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2020-11-18 11:40:57 +08:00
Wang Panzhenzhuan
24959aba90 arm64: configs: rockchip_defconfig: enable gc2385 
This is needed for rk3566 rk817 tablet.

Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: I4180aae4e40677f456ee10aff8760288a1fd79bc
 2020-11-18 11:26:08 +08:00
Shawn Lin
266ef3dda3 phy: rockchip: naneng-combphy: Add RMJ control for PCIe 
Change-Id: Iaf2d8fab379aa77dc127778b3943000b0e4bf2a6
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2020-11-18 10:27:08 +08:00
Elaine Zhang
dc3e6cd531 clk: rockchip: rk3568: Make rkvdec aclk and core clk in same parent clk 
Rkvdec must used in same-origin mode.

Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I97590a287b7b92d1074a47405be8ac65d084d328
 2020-11-18 10:08:07 +08:00
Allon Huang
62f4cd623d media: i2c: imx323: add RKMODULE_GET_BT656_INTF_TYPE interface 
Signed-off-by: Allon Huang <allon.huang@rock-chips.com>
Change-Id: I1642d4a8c05e4d9058ace7bb07bd6215dc85b0be
 2020-11-18 10:06:50 +08:00
Wang Panzhenzhuan
88fe34b61f arm64: dts: rockchip: rk3566-rk817-tablet: add camera configs 
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: I72df5442d5a3882f798840c636d03fefda425c0f
 2020-11-18 10:05:39 +08:00
Shawn Lin
30cbc746c3 arm64: dts: rockchip: rk3568-pinctrl: Adjust sdmmc0 drive strength 
Change-Id: I56fb5c77978355dadf883e32ad9b51c92345e52f
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2020-11-18 10:04:02 +08:00
Ren Jianing
fe9e64f566 phy: rockchip: naneng-combphy: improve phy init for rk3568 
1. Add clks enable and disable control.
2. Do PCIe/USB3/SATA phy init in their own helper.
3. Select ref clk according to ref clk rate for RK3568
4. Set SSC clk rate and SSC derection for the USB3 of RK3568.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: If2959147cfe9f799c88c31ef7cefbccc872a3bf4
 2020-11-18 09:58:19 +08:00
Huang zhibao
031f29082c arm64: dts: rockchip: rk3568-nvr enable hdmi sound 
Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: I7cd497fba1bb87f9b7d42105adcdcf954fcd7e7a
 2020-11-18 09:50:37 +08:00
Huang zhibao
53fdaf6ccc arm64: dts: rockchip: update configs for rk3568-nvr-demo-v10 
1. config gpio leds
2. enable sata1 and sata2

Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: Ifbcbc89bce00a774073d2233d5c1f445cb0123d0
 2020-11-18 09:50:15 +08:00
Wu Liangqing
a6529c473d arm64: dts: rockchip: rk3566-tablet: gslX680 set IRQ_TYPE_LEVEL_HIGH 
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
Change-Id: I6b6453e7cc6f6ae919b8217a45dd4403997f3e03
 2020-11-18 09:48:33 +08:00
Jianqun Xu
16a26f00a9 pinctrl: rockchip: fix rk3568 route mux table 
Change-Id: Ic3f85815d683fd3335d5ac0eca3b9f30b1638d48
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2020-11-18 09:12:48 +08:00
Weiguo Hu
3879e152ce net: wireless: rockchip_wlan: realtek wifi: fix buffer overflow issue in rtw_ioctl_wext_private 
References: CNVD-C-2020-263891
Signed-off-by: Weiguo Hu <hwg@rock-chips.com>
Change-Id: If80c197d9e806a04a14a3a8dbe195942deed46eb
 2020-11-17 18:40:00 +08:00
Jianqun Xu
a24abc2faf pinctrl: rockchip: remove bank valid about gpio 
Change-Id: If8c8de4eae0bac109e3c81136530cf0c1887fc65
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2020-11-17 18:32:25 +08:00
Wang Panzhenzhuan
40836ce7c7 arm64: dts: rockchip: rk3568: fix rkcif_mmu error 
error log:
[  352.947003] rkcif_dvp: Allocate dummy buffer, size: 0x00075300
[  352.947160] rk_iommu fdfe0800.iommu: Error during raw reset.
MMU_DTE_ADDR is not functioning
[  352.947236] rkcif_dvp: Failed to get runtime pm, -14

Signed-off-by: Allon Huang <allon.huang@rock-chips.com>
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: I1eab7daed218a40e2d6f14499e1e24da927953e5
 2020-11-17 18:26:13 +08:00
Shawn Lin
136622acc9 arm64: dts: rockchip: rk3568: Increase PPLL to 200MHz 
ppll is for combophy refclk to lock, and it should support
25M/100M. So we need to increase it to 200MHz.

Change-Id: I224a221296ed074a60354d65e7c678de4f7f7120
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2020-11-17 18:20:20 +08:00
Bin Yang
02cefed5ae arm64: dts: rockchip: update usb configs for rk3566-rk817-tablet 
1. set dr_mode to otg for usbdrd_dwc3.
2. remove usbhost30 and u2phy0_host, these are unused.

Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Change-Id: Ia93df0660552bb54211252f4c35d72d8a1ef7934
 2020-11-17 15:28:24 +08:00
Andy Yan
866abfdc6d drm/rockchip: vop2: Change scale factor calculate algorithm 
Vop2 can't share the same scale factor calculate
algorithm with rk3399 on some situation, even they
use the same scale algorithm.

Change-Id: I90dd39b2482d39d56ee94046830facc4d20f5cb2
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2020-11-17 15:20:22 +08:00
Bian Jin chen
0c17853c97 dm table: Avoid null pointer dereference 
Test: vts_libdm_test

Unable to handle kernel access to user memory outside uaccess routines
at virtual address 0000000000000018
[   83.108561] Mem abort info:
[   83.108896]   ESR = 0x96000005
[   83.109191]   Exception class = DABT (current EL), IL = 32 bits
[   83.110203]   SET = 0, FnV = 0
[   83.110505]   EA = 0, S1PTW = 0
[   83.110894] Data abort info:
[   83.111182]   ISV = 0, ISS = 0x00000005
[   83.111537]   CM = 0, WnR = 0
[   83.111929] user pgtable: 4k pages, 39-bit VAs, pgdp = 00000000cff2854e
[   83.112534] [0000000000000018] pgd=0000000033f28003, pud=0000000033f28003, pmd=0000000000000000
[   83.113403] Internal error: Oops: 96000005 [#1] PREEMPT SMP
[   83.113912] Modules linked in: 8723cs
[   83.114257] Process vts_libdm_test (pid: 1985, stack limit = 0x000000007ea1bacc)
[   83.114923] CPU: 3 PID: 1985 Comm: vts_libdm_test Not tainted 4.19.154 #41
[   83.115534] Hardware name: Rockchip rk3326 863 rkisp1 board (DT)
[   83.116082] pstate: 40400005 (nZcv daif +PAN -UAO)
[   83.116534] pc : __pi_strncmp+0x24/0x208
[   83.116908] lr : dm_table_add_target+0x184/0x3bc
[   83.117326] sp : ffffff8012bcbb70

Fixes: 531fc5e280 ("dm: add check target device probe completely")
Signed-off-by: Bian Jin chen <kenjc.bian@rock-chips.com>
Change-Id: Icb943c4d1dfe116b3b39f4cd77b2eda232de65fe
 2020-11-17 15:20:08 +08:00
Huang zhibao
64e1eacb73 arm64: dts: rockchip: Add support for rk3568-nvr demo board 
Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: Iefe072f9b18e5e8c0103391f782aa510b6c326e0
 2020-11-17 14:56:01 +08:00
Guochun Huang
35d1482625 drm/rockchip: dsi: enable hclk before pclk 
There is a risk of access failure, if pclk
is enabled without enabling hclk in rk3568.

Change-Id: I02c2a0d8ad6c0d2c6649ee16ab50dda0da542aac
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
 2020-11-17 14:54:41 +08:00
Wyon Bi
ad3cad3616 drm/rockchip: analogix_dp: Covert to use bulk clk 
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I79466efdcce0c0495a67948f3d36a03e39f4b9ed
 2020-11-17 14:28:12 +08:00
Wyon Bi
00425aeadd arm64: dts: rockchip: rk3568: Fix edp clock 
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: If35282b9f0fc740f174e240803de6ebc2a049c66
 2020-11-17 14:24:44 +08:00
Guochun Huang
f8956385bc arm64: dts: rockchip: rk3568: dsi add HCLK_VO clk 
Change-Id: Ib900d0c2028599d55c2ee03dac74172d1b403a6c
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
 2020-11-17 14:12:57 +08:00
Jianqun Xu
0ec895a5ac regulator: fix regulator_summary name show issue 
Before this patch:
vcc_1v8                    0    3      0  1800mV     0mA  1800mV  1800mV
   fdc20000.syscon:io-domains                                     0mV     0mV
   fdc20000.syscon:io-domains                                     0mV     0mV
   deviceless                                                0mV     0mV
vdda0v9_image              0    1      0   900mV     0mA   900mV   900mV
   deviceless                                                0mV     0mV

With this patch:
vcc_1v8                                        0    3      0  1800mV     0mA  1800mV  1800mV
   fdc20000.syscon:io-domains-vccio6                                             0mV     0mV
   fdc20000.syscon:io-domains-vccio4                                             0mV     0mV

Change-Id: Iaae22f406bb75027279eeb234b570edee952abc4
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2020-11-17 11:28:52 +08:00
Lee Jones
35dbcb55c6 UPSTREAM: regulator: consumer: Supply missing prototypes for 3 core functions 
regulator_suspend_enable(), regulator_suspend_disable() and
regulator_set_suspend_voltage() are all exported members of the
API, but are all missing prototypes.

Fixes the following W=1 warning(s):

 drivers/regulator/core.c:3805:5: warning: no previous prototype for ‘regulator_suspend_enable’ [-Wmissing-prototypes]
 3805 | int regulator_suspend_enable(struct regulator_dev *rdev,
 | ^~~~~~~~~~~~~~~~~~~~~~~~
 drivers/regulator/core.c:3812:5: warning: no previous prototype for ‘regulator_suspend_disable’ [-Wmissing-prototypes]
 3812 | int regulator_suspend_disable(struct regulator_dev *rdev,
 | ^~~~~~~~~~~~~~~~~~~~~~~~~
 drivers/regulator/core.c:3851:5: warning: no previous prototype for ‘regulator_set_suspend_voltage’ [-Wmissing-prototypes]
 3851 | int regulator_set_suspend_voltage(struct regulator *regulator, int min_uV,
 | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Change-Id: I1ccdd34e5a7c42976472a00b4b17547bd741509e
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20200625163614.4001403-2-lee.jones@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit da6690767c)
 2020-11-17 11:24:32 +08:00
Andy Yan
aa049c3686 drm/rockchip: vop2: Add rb swap for yuv444 output 
According to the test on HDMI, when vop do csc(rgb2yuv444),
it need a rb_swap to show right color. But yuv420 don't
need to do so.

Change-Id: I16c7530b015bd67a584cf39304df9b9f5b0d7a29
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
 2020-11-17 11:15:35 +08:00
Sugar Zhang
1b8e5ce927 arm64: dts: rockchip: rk3568: Move property '#sound-dai-cells" into dtsi 
Change-Id: Ia4a24f5730c8e985e7ec59d5f9174a7ce3d0e2f8
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
 2020-11-17 10:56:47 +08:00