The otg id voltage is provided from usb2 phy power. On some
rockchip platforms (e.g. rk3399), the usb2 phy power will be
turned off when enter pm suspend, this will trigger id fall
interrupt. But current code enable the ID interrupt consistently,
it may result in the mistake of ID changing operation even if
the state of ID pin is not changed. So disable ID irq when
suspend and enable when resume.
Change-Id: Icac35f13861fd639e4b422b31182a68add73836d
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch creates an usb2 phy attribute group and
provides an attribute "otg_mode" for otg port to
force otg mode independently of the voltage of otg
id pin.
In order to implement the force mode function, we can
select otg plug indicator output (AKA iddig) from GRF,
and set GRF USB otg plug indicator to "0" or "1" to
control iddig status.
We only support rk322x/rk3328 to force otg mode for
the time being.
And we need to disable usb auto suspend function if
we want to force otg mode. Add 'usbcore.autosuspend=-1'
in cmdline to disable usb auto suspend.
Usage:
[1] Force host mode
echo host > /sys/devices/platform/<u2phy dev name>/mode
[2] Force peripheral mode
echo peripheral > /sys/devices/platform/<u2phy dev name>/mode
[3] Force otg mode
echo otg > /sys/devices/platform/<u2phy dev name>/mode
Legacy Usage:
[1] Force host mode
echo 1 > /sys/devices/platform/<u2phy dev name>/mode
[2] Force peripheral mode
echo 2 > /sys/devices/platform/<u2phy dev name>/mode
[3] Force otg mode
echo 0 > /sys/devices/platform/<u2phy dev name>/mode
Change-Id: I875b60b0390e3bd9af34b740cba8f5d53e1df752
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
There are some race conditions related to phy power on/off
and otg charger detection work, otg sm work. I can find at
least three race conditions at present.
Race condition[1]:
The first race condition involving phy power on/off which
may be caused by the following case.
Test on rk3399 evaluation board Type-C0, connect to PC usb
port with Type-C cable, then phy power on/off operation may
be done twice because of race condition between phy driver
and usb controller driver.
CPU 0:
- rockchip_usb2phy_bvalid_irq()
- rockchip_usb2phy_otg_sm_work()
- detect connect to PC usb, do phy power on
- rockchip_usb2phy_power_on()
CPU 1:
- dwc3 driver do runtime resume process
- dwc3_runtime_resume()
- dwc3_core_init()
- phy_power_on()
- rockchip_usb2phy_power_on()
Although we use a suspended flag in rockchip_usb2phy_power_on()
to avoid doing the same things twice, but it's not enough to
prevent race condition if phy driver and usb controller driver
access the rockchip_usb2phy_power_on() at the same time. This
race condition may cause clk management unbalanced.
Race condition[2]:
The second race condition related to phy power on/off and otg
charger detection work. We need to keep the usb phy staying in
suspend mode when do usb charger detection. But now it don't
have any protection to prevent the other threads to operate phy
during charger detection.
The problem can also be easily reproduced on rk3399 evaluation
board Type-C0 when connect to PC usb port with Type-C cable.
CPU 0:
- rockchip_chg_detect_work()
- power off phy and start to do charge detection work
CPU 1:
- dwc3 driver do runtime resume process
- dwc3_runtime_resume()
- dwc3_core_init()
- phy_power_on()
- power on phy again
This race condition may cause charger detection and later usb
enumeration abnormally.
Race condition[3]:
The third race condition involving otg sm work. The otg sm
work can be interrupted by bvalid irq, and the bvalid irq
handler rockchip_usb2phy_bvalid_irq() will do otg sm work,
which may cause unknown error.
This patch uses mutex lock to protect the phy operations,
otg charger detection work and otg sm work.
Change-Id: Ic6845a10b3e69fe9ae6cf0b2d4e2beb098232abd
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The USB 2.0 PHY may lose tuning config after resume if the
PD turn off its power when suspend. So we need to tune USB
2.0 PHY again when resume.
Change-Id: Ib34de165ccd7d22598e77e5ac0fed1233e7adba0
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
According to USB 2.0 Spec Table 7-7, the High-speed squelch
detection threshold Min 100mV and Max 150mV, and we set USB
2.0 PHY0 and PHY1 squelch detection threshold to 150mV by
default, so if the amplitude of differential voltage envelope
is < 150 mV, the USB 2.0 PHYs envelope detector will indicate
it as squelch.
On RK3399 box, if we connect usb device with a 4 meter cable,
we can see that the impedance of U2 cable is too big according
to the eye-diagram test report, and this cause serious signal
attenuation at the end of receiver, the amplitude of differential
voltage falls below 150mV.
This patch aims to reduce the PHY0 and PHY1 otg-ports squelch
detection threshold to 125mV (host-ports still use 150mV by
default), this is helpful to increase USB 2.0 PHY compatibility.
Change-Id: Iec8b4043a3440d6f2a5fb18ff59ac0f4988019e9
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The commit c590056b6a ("phy: rockchip-inno-usb2: usb remote
wakeup support") power on otg phy in linestate irq handler,
this will cause usb peripheral fail to connect to PC in the
following case:
1. enable otg linestate irq
2. set system enter deep sleep
3. wakeup system by power key
4. connect usb peripheral to PC, pull up D+ to ~3V, trigger
linestate irq and power on otg phy.
5. usb peripheral do BC1.2 detect, but PC try to enumerate
the usb peripheral at the same time and fail at last.
Actually the usb controller drivers (e.g. dwc3 driver)
and otg_sm_work can manage the otg phy power consumption, so
it doesn't need to power on otg phy in linestate irq handler.
Change-Id: Ifd78e4d44ab96f07f75f063ed20af153b4027028
Signed-off-by: William Wu <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This adds amend logic of sm work to compatibly support some legacy SoCs,
because _host_utmi_linestate_ and _host_utmi_hostdisconnect_ GRF status
bits which are required for host sm work were not introduced in these
SoCs.
Change-Id: Ib4f499f592618930ac5016a63b7a530674aa6005
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The usb controller may need to disconnect vbus to trigger disconnect
process or connect vbus to trigger connect interrupt by software. But
current code does not realize the interface. This patch add set mode
function in usb2 phy driver, connect vbus in device mode and disconnect
in other mode.
Change-Id: I49b4180af2f47156a3f4d31f4539f3e444f89a62
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Usb-controller can invoke phy_power_on/off in its suspend/resume
process, so usb-phy need not do it again.
This adds remove phy_power_on/off in its suspend/resume cases.
Change-Id: Ice30e79ffba8116ca9bfae344c7ea232f6580130
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The linestate change interrupt may occur during suspend if port is
not connected. This patch pull down dp/dm when suspend.
Change-Id: I31e992727ea63efbda4ecec7ad3af02626eceb44
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
If extcon cable state is EXTCON_USB_VBUS_EN, it also means
that otg host connected, don't need to do charge detection.
Change-Id: Ie7c97c4cd0cfd2688edbfb3bbff93d2f58e9ef9a
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Add EXTCON_USB_VBUS_EN cable and change EXTCON_USB_HOST to
EXTCON_USB_VBUS_EN cable to control vbus.
Change-Id: I2e7c6111f723e425bd4c156e803cb6a1a9f17511
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Add the new extcon EXTCON_USB_VBUS_EN to enable
vbus output.
Change-Id: I83fb75b2a82ad617dc292967bb4917bbfbcb84cb
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Id pin interrupt not occur when system start, so we need to check
id pin value when u2phy probe and set cable to host if the value
is high.
Change-Id: I333d5cae2463a159a18b455550a76ebcac704c44
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
No need notify charging-external-connector state when otg host connect.
Change-Id: I1d5c6e4fb2ad504f169ef0fd5b82b06f31783922
Signed-off-by: Binyuan Lan <lby@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
In the case of platform designed in usb2.0 only mode, which
the dwc3 controller connect without fusb302 and type-c phy
does not work, the u2phy need to support hot plug and detect
otg mode, this patch add support of otg function in this mode.
Change-Id: I428a4f6d17d847c6114d124733e62c0a6236b94e
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The otg_sm_work is a OTG state machine delay work. It will hold
a wake lock if SDP cable or CDP cable is attached, and release
the wake lock if cable dettached. If usb controller(e.g. DWC3)
call phy exit When USB cable is dettached and cancel otg_sm_work,
it will cause the usb phy keeping hold of wake lock.
Change-Id: Ie6a89e481b8d4999a996083709bacc5be901805a
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
If detect a SDP charger type, we retry twice more to avoid
DCP falsely identified as SDP due to hardware signal error.
Change-Id: I1bf7bd076cd7767938f6944f1156daa7e64870e4
Signed-off-by: Feng Mingli <fml@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This adds support host-port on rk3368 SoC and amend phy Documentation.
Change-Id: I49a2efe37aad8b34505e4dac08336dc4231f4669
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch adds a method to tuning phy with the following
parameters to improve usb driver strength and increase usb2
compatibility.
1. Set max ODT compensation voltage and current tuning reference.
2. Set max pre-emphasis level.
3. Disable the pre-emphasize in eop state and chirp state
to avoid mis-trigger the disconnect detection and also
avoid hs handshake fail.
We don't enable the phy tuning by default. If you want to
tuning phy, you can add a property "rockchip,u2phy-tuning"
in u2phy node, like this:
&u2phy0 {
rockchip,u2phy-tuning;
};
&u2phy1 {
rockchip,u2phy-tuning;
};
Conflicts:
Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.txt
Change-Id: Iaa70e2ad3d5d06662be6c05e4d20784e5bb85ae9
Signed-off-by: William Wu <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This adds support usb remote wakeup both host-port and otg-port,
each port can detect linestate irq then wakeup the whole system.
Conflicts:
drivers/phy/rockchip/phy-rockchip-inno-usb2.c
Change-Id: I5efcf958131827548954deb9360b9e98aa4bd0bc
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch does not aim to upstream, just use locally.
If needed, the different SoC can register its own callback function
to tunning the default parameters of phy.
Conflicts:
drivers/phy/rockchip/phy-rockchip-inno-usb2.c
Change-Id: I19b2a4f9e0cb04b139dd64eae1c856fbe9142665
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Some platforms (e.g. RK3399 BOX board) otg port connector
interface is not standard, that is a Type-A connector with
vbus always powered on, looks like to work as host mode,
however, the otg port still need to support DRD mode.
In the current code, if otg vbus is always powered on, it
will cause USB2 PHY to detect a floating charger in error
case and power off USB2 PHY. This patch adds a new property
"rockchip,vbus-always-on" to fix this issue. With this patch,
we handle this case as otg host only mode, and avoid to do
charger detection and power off USB2 PHY.
Conflicts:
drivers/phy/rockchip/phy-rockchip-inno-usb2.c
Change-Id: I69e5e87021f3f2d654793e547264aec55ac664ef
Signed-off-by: William Wu <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Rockchip USB2 phy provides utmi_avalid and utmi_bvalid for
user to check UTMI vbus status. Generally, both of them can
reflect the vbus status correctly, and the utmi_bvalid has
higher sensitivity, so we select the utmi_bvalid to get vbus
status by default.
But some special SoCs may not provide utmi_bvalid, so we
need to select utmi_avalid in this case.
Conflicts:
drivers/phy/rockchip/phy-rockchip-inno-usb2.c
Change-Id: I0d47c2237f852cb67ebd82fe2673b2bd2e6ccce6
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This fix the existing compile error:
Error: arch/arm64/boot/dts/rockchip/rk3308.dtsi:1765.12-13 syntax error
FATAL ERROR: Unable to parse input tree
And also from the upstrem[0][1], some people don't like the
pointless MACRO RK_FUNC_n.
All the modifications done with sed:
sed -i -e 's/RK_FUNC_GPIO/0/' arch/arm64/boot/dts/rockchip/rk3308*
sed -i -e 's/RK_FUNC_//' arch/arm64/boot/dts/rockchip/rk3308*
[0] https://patchwork.kernel.org/patch/9625173/
[1] https://patchwork.kernel.org/patch/9626883/
Change-Id: Icb7c36fb6bd152628ddb911fc221f65e105e5839
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
because currently mclk is handled by codec side, so the
associated pinctrl should be handled by codec too.
Change-Id: I55db6e9a0181cae0cb414b9dcacae7ff0214b50c
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
to fix up :
[ 0.000000] clk: couldn't get clock 4 for /clock-controller@ff760000
[ 0.000000] rockchip_clk_of_add_provider: could not register clk provider
The cause of the error:
struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
const char *con_id, bool with_orphans)
{
/* This is to allow this function to be chained to others */
if (!hw || IS_ERR(hw))
return (struct clk *) hw;
if (hw->core->orphan && !with_orphans)
return ERR_PTR(-EPROBE_DEFER);
return clk_hw_create_clk(hw, dev_id, con_id);
}
if clk is orphan and not have the with_orphans flag, it will
register clk provider failed.
Change-Id: I87ca9ec087611a5425545bfc857b09d8438218b5
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This patch adds "snps,xhci-trb-ent-quirk" for DWC3 controllers
in RK1808/RK3328/RK3399/RK3399pro-npu.
Change-Id: I708f62747150316d66459f02b399d7c9b2667636
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
It has been reported that xHCI on this SoC really cannot
sleep without extraordinary delay. This quirk can ensure
the xHCI enter the Halted state after the Run/Stop (R/S)
bit is cleared to '0'.
Change-Id: Ibccf0c5c2da4533817b998b523e3a3a09ed7dcea
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
rk previous SOCs such as rk3126 have no tsadc module, so a virtual tsadc is
implemented to control the thermal problem.
the virtual tsadc is designed on considering 2 factors, one is heating
modules' heating time and the working frequences, the other one is current
leval monitored by coulometer.
Change-Id: I0c7d8b952004d4f7918a41c925c50d38aaa65673
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Due to 32k clock jitter, tsadc will wrongly report a very
high temperature, that is a temperature-jump. This may lead
to an abnormal OS reboot. A filter function is added to
predict the true temperature.
Change-Id: I5b5641efe8e64b4058a604f274350b1e94584fa6
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
In order not to affect other clocks, remove the apll from the
parent list of other clocks and only core, mac and lcdc can
select apll as parent.
Change-Id: I58b995f8ccf69c6564f74b5823f618a186030d70
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Some clocks may get disabled as a side effect of another clock
being disabled, because have no consumers. Says the dclk_hdmi's parent may
change from apll to gpll, but the apll's son clocks are very less.
Change-Id: I4fb4e5fdf83a8f73979b50dbcf4f3e4543896fcf
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
1. The first parent name of sclk_cif_out_src is wrong, it is
"sclk_cif_src".
2. The MUX configuration for sclk_cif_out_src is wrong, it should
be muxdiv_offset=29, mux_shift=2, mux_width=1.
Change-Id: I36a0ec0791afdef398d37ac8b92b7831619fb01b
Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The clock hevc core will be used to drive the hevc decoder.
Change-Id: Ic1298ce1edd07f86e5c243e3a2c9876481f4cba9
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
npll is just for dclk_vop, others clk not allowed to set npll as parent.
Change-Id: I11e1770acab5486acaebafd56a0c57847f7f533c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
