Ensure the pclk is enabled when register access occurs.
Change-Id: Id108a04aed8424725dcc02dec9fe46bfc724c09b
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Background:
- EDP software register bank is on the EDP 24m clock domain;
- CPU access EDP software register bank, need to go through EDP APB
read/write bus and EDP internal read/write bus;
- EDP APB read/write bus is on the EDP pclk clock domain;
- EDP internal read/write bus is on the EDP 24m clock domain;
- Asynchronous logic circuit is added between APB read/write bus and
Internal read/write bus;
Issue:
There is a bug on the Asynchronous logic circuit between APB read/write
bus and Internal read/write bus; This bug will be random to cause the
following wrong control/address signals sequence happen;
- For write, maybe wrong register address is wrote in;
- For read, maybe wrong register address is read out;
Workaround:
- For CPU write EDP register operation, write any register need
following three steps,
1): Read EDP_BASE+0x00 dummy register firstly, latch the dummy
register address on Reg_Address bus, to avoid next step write to
wrong register to cause function register overrun;
2): 1st time to write the EDP register you want to operate,
to latch the real write address on Reg_Address bus;
3): 2nd time to write the EDP register you want to operate,
to make sure the data is write on the real write address;
- For CPU read EDP register operation, read any register need following
two steps,
1): 1st time to read the EDP register you want to operate, to latch
the real read address on Reg_Address bus;
2): 2nd time to read the EDP register you want to operate, to make
sure the data is read out from the real read address;
Change-Id: I4a87d3883efe94d32ccf8809edb5b9d869670d2d
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
The interrupt is requested before the device is powered on and
it's value in some cases cannot be reliable. It happens on some
devices that an interrupt is generated as soon as requested
before having the chance to disable the irq.
Change-Id: I889c069239d005ab0a3fb4eb36123608ec81d9ab
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
The video BIST function of the DP_TX generates arbitrary video formats
internally according to the specified format configuration and selection.
These BIST video formats simplify DP_TX debugging.
Change-Id: Ia019c8f40fdd4ebea3e5250be8e2c15540481a6c
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Amend to fix the UAC2 gadget could not be identified on Windows 10 OS.
Change-Id: I992af23ab4ac2740a33621d9c3c47368f5135710
Fixes: 486bd80e78f4 ("UPSTREAM: usb: f_uac2: adds support for SS and SSP")
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The driver reads OTP value from SoC to provide the OPP framework
with required information. This is used to determine the voltage and
frequency value for each OPP of operating-points-v2 table when it is
parsed by the OPP framework.
Change-Id: Iec5a4ff05a4829fdbc3535f94e92759d4238623d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Initially, the helper dev_pm_opp_get_opp_table() was supposed to be used
only for the OPP core's internal use (it tries to find an existing OPP
table and if it doesn't find one, then it allocates the OPP table).
Sometime back, the cpufreq-dt driver started using it to make sure all
the relevant resources required by the OPP core are available earlier
during initialization process to properly propagate -EPROBE_DEFER.
It worked but it also abused the API to create an OPP table, which
should be created with the help of other helpers provided by the OPP
core.
The OPP core will be updated in a later commit to limit the scope of
dev_pm_opp_get_opp_table() to only finding an existing OPP table and not
create one. This commit updates the cpufreq-dt driver before that
happens.
Now the cpufreq-dt driver creates the OPP and cpufreq tables for all the
CPUs from driver's init callback itself.
Change-Id: Icd477646eb0eefeb01266e21064824d1b5ed6b46
Tested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
(cherry picked from commit 873c9851eb)
1. support get pvtm from otp.
2. adjust opp-table by mbist_vmit which is get from otp.
Change-Id: Ie3703873880b65b2af03ae474065d541c7f9d605
Signed-off-by: Liang Chen <cl@rock-chips.com>
Add the ability to parse panel-desc data from the devicetree if it's
not hard-coded data.
Change-Id: I474940282657c9aa03568b9f98916125784d9fcf
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
1. limit vmin of cpu/gpu/npu/logic by mbist_vmin.
2. raise vdd_logic when npu run at 1.0GHz or venc run at 400MHz.
3. disable npu@1.0GHz and venc@400MHz by default.
4. reduce vdd_logic for the chips with big leakage.
5. adjust low-temp-adjust-volt table.
Change-Id: If7ce6f010422d20e2dfd643a6894fa7304e6372f
Signed-off-by: Liang Chen <cl@rock-chips.com>
Possibly, provider driver initialization is later than
consumer driver. Use function subsys_initcall to initialize
NVMEM provider early to ensure NVMEM consumer doesn't need
to -EPROBE_DEFER.
Change-Id: I817aa44c3b34d2fdf44148e6b9649ceed76d8f1f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Possibly, provider driver initialization is later than
consumer driver. Use function subsys_initcall to initialize
NVMEM provider early to ensure NVMEM consumer doesn't need
to -EPROBE_DEFER.
Change-Id: Ibaea188390a54d55eca2aa3585cace7bb8f37bb3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
As npll rate may be changed according to vopl dclk rate on px30.
Change-Id: I4abc042b49ee06436ba5d69dc8adfa9460da37f7
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
NPLL should provide clock for vopl dclk on px30, and its rate will be
changed according to vopl dclk rate, so GPU can't use npll as parent
on px30.
Change-Id: Ib2c8c57020405bcd14070dcd7bc71cbfe18230e3
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
DPTPHYT22ULP is designed for chips that perform eDP/DP data
communication while operating at low power consumption.
The main link is a multi-gigabit transmitter macro which
enable speed up to 4.0Gbps data transmitter with optimized
power and die size, also it can be easily fabricated and
implemented in a video system. The AUX channel is a halfduplex,
bidirectional channel consisting of one differential pair,
supporting the bit rate of about 1Mbps.
Macro consists of multi-main link transmitter channels,
AUX channel, one PLL and bias-gen unit. The main link
transmitter performs dedicated P2S, clock generator,
driver with preemphasis and self-test. Each of the channels
can be turned off individually.
Change-Id: Idf58991ff1bdd4557c4cfadf2dc047e95eca7668
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
The Rockchip GPIO and pin control modules are only present on Rockchip
SoCs. Hence add a dependency on ARCH_ROCKCHIP, to prevent asking the
user about this driver when configuring a kernel without Rockchip
platform support.
Note that before, the PINCTRL_ROCKCHIP symbol was not visible, and
automatically selected when needed. By making it tristate and
user-selectable, it became visible for everyone.
Change-Id: Ibaa8fddc0f667711bd6fc82fe1865cf65720c1c3
Fixes: be786ac5a6 ("pinctrl: rockchip: make driver be tristate module")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20210316134059.2377081-1-geert+renesas@glider.be
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit febb4ee23a)
reason: In rk356x, due to the hardware, vepu and jpegd should
disable auto freqence.
Change-Id: I2da5b5a7fc3b86180aef28b378a7b651e31a6b7a
Signed-off-by: Ding Wei <leo.ding@rock-chips.com>
When using 24MHz reference clock, some devices can't identify
the SATA PM chip, And the signal quality is not as good as 100MHz.
so change the reference clock to 100MHz.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: If7d951a0b77d503f9faf1c1f88c78a9e07471e47
In order to silent the warning below:
mmc0: unspecified timeout for CMD6 - use generic
Fixes: 4734c45258 ("mmc: core: don't check card status when flushing cache")
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I561fd8592c646a61d22b04e27a0fc0a6c9b01f4e
Both rk3568' spi is compatible with rk3036's spi design.
Change-Id: I952beb57c151e77165db781bc17ec782b6bc62a4
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
the sub_dev will be update by list_for_each_entry() and return !NULL
error pointer when no found subdev;
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I8d7db3b66c6c57b986a42cac9ed6eca53b72611e
https://android.googlesource.com/kernel/configs
commit 46f8bc810fbe ("Finalize min LTS version for S.")
android-base.config and android-base-conditional.xml:
-# CONFIG_RD_LZ4 is not set
+CONFIG_USERFAULTFD=y
+CONFIG_SHADOW_CALL_STACK=y
+CONFIG_XFRM_MIGRATE=y
+CONFIG_SONY_FF=y
+CONFIG_ANDROID_BINDERFS=y
+CONFIG_CRYPTO_CHACHA20POLY1305=y
+CONFIG_CRYPTO_XCBC=y
+CONFIG_KFENCE=y
from gki_defconfig:
+CONFIG_KFENCE_SAMPLE_INTERVAL=500
+CONFIG_KFENCE_NUM_OBJECTS=63
RD_LZ4:
Support future decompression of LZ4-compressed ramdisk images.
USERFAULTFD:
Patches for SELinux support and kernel page-fault restriction in
userfaultfd have been backported.
So from security perspective it should be safe to enable it in Android.
XFRM_MIGRATE:
To be able to update addresses of an IPsec SA, as required by
supporting MOBIKE
CHACHA20POLY1305 and XCBC:
To be able to use ChaCha20Poly1305 and AES-XCBC in IPsec
CONFIG_KFENCE_NUM_OBJECTS controls the constant memory overhead that
KFENCE introduces for its memory pool. By default it is 255 objects
(2Mb extra memory), but since concerns have been raised that low-memory
devices may not afford that, we are lowering the number of objects
to 63 (512Kb extra memory).
So far we haven't seen Android devices allocate more than 50 KFENCE
objects. Should the kernel exhaust the pool, KFENCE will stop allocating
new objects and fall back to SLAB/SLUB until one of the objects is
freed.
An immediate consequence of reducing the pool size is that a freed
KFENCE object will be reused 4x times faster, effectively reducing the
probability of detecting a use-after-free. Since KFENCE is a best-effort
error detection tool, not a use-after-free mitigation mechanism, we
believe this should not be problematic.
enable KFENCE by setting the sample interval to 500ms
It is still possible to disable KFENCE at boot time using
kfence.sample_interval=0.
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I061f3caf0d09adfd4e0c322853aeff5af8ba63a5
According to commit f382fb0bce ("block: remove legacy IO schedulers").
-# CONFIG_IOSCHED_DEADLINE is not set
-CONFIG_CFQ_GROUP_IOSCHED=y
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: Ia20d8fe921b4ff0e4b8507ef665cae865704f717
