Add a ddrc clock into clk branches, so we can do ddr frequency
scaling on rk3368 platform in future.
Change-Id: Ie7fd2e8d8bdf8b9ff843ca13e848f772adaa109a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
On rk3368, let a mcu scaling ddr clock via SCPI (System Control and
Power Interface) APIs.
Change-Id: I95342b876caad991e6d1319c5e4ec793365c7981
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
CPLL and NPLL is used for vop dclk, sync rate flag would cause
loader display abnormal.
Change-Id: Ia170a8d0b7d1f39e2c9dcbc10b5d33fd1886d5f7
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reference the newly added efuse clock-ids in the clock-tree.
Change-Id: Ibbef52bcc44d006ab48e6f1f874e3bc88c681bd6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
While the CSV3 field of the ID_AA64_PFR0 CPU ID register can be checked
to see if a CPU is susceptible to Meltdown and therefore requires kpti
to be enabled, existing CPUs do not implement this field.
We therefore whitelist all unaffected Cortex-A CPUs that do not implement
the CSV3 field.
Change-Id: I1af7495be64d40a1e05a201f19e5f066b0d4bcc7
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit 2a355ec257)
From "CPU selection" to "Rockchip CPU selection".
Change-Id: I5d9368ca6eb9ba60cd4c33fdd703775a328e9da0
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Single entry is for target voltage and three entries are for
<target min max> voltages. Change cpu opp-microvolt form one entry to
three entries and set maximum acceptable voltage to a high value so that
regulator device can supply multiple consumers at the same time.
Change-Id: I3a0dc4e161bae33e36b232c36a0a05a3102359ef
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
stress test:
1. Antutu, use governor simpleondemand
2. Need for Speed, use governor simpleondemand
3. Glmark2, use userspace, scanning frequency
Change-Id: Ibe27380e582b193d900b0d55da3567ce553c32df
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Compiling the DT file with W=1, DTC warns like follows:
Warning (unit_address_vs_reg): Node /opp_table0/opp@1000000000 has a
unit name, but no reg property
Fix this by replacing '@' with '-' as the OPP nodes will never have a
"reg" property.
Change-Id: I5748be7888db149633c3980c3f5e9715cd256a52
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Only 200MHz, 300MHz, 400MHz, 528MHz, 600MHz, 666MHz, 732MHz and
800MHz are available at present.
Change-Id: I48ed7e6e6f636389fbc239b1cca201f5c5f19d7a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
It would be better to name OPP nodes as opp@<opp-hz> as that will ensure
that multiple DT nodes don't contain the same frequency. Of course we
expect the writer to name the node with its opp-hz frequency and not any
other frequency.
And that will let the compile error out if multiple nodes are using the
same opp-hz frequency.
Change-Id: I8c77646329e39390fb135d4d75d34893a8168876
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Add a new dtsi file - rk3399-opp.dtsi, to configure opp-tables
for cpu, gpu and dmc.
Add rk3399-early-opp.dtsi for board with ES1, which need limit
frequency for cpu, gpu and dmc.
Change-Id: Ib57761fd5f405b0e79039d7a01e6e023d6f5dc2c
Reviewed-by: Finley Xiao <finley.xiao@rock-chips.com>
Reviewed-by: Huang, Tao <huangtao@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
to slove the display shaking, when uboot logo display to kernel show.
Change-Id: I804aa09f24bc4fa7b6314a7a5487f0ee1a321724
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
pclk_perihp_grf and pclk_vio_grf is for some grf regs read and write,
mark it as critical and it never turns off.
Change-Id: If9465334b9168b4376a7ac95d5f08e389048409f
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
others clk change it's parent from cpll to dummy_cpll.
the vop's parent just vpll and cpll,
make sure each vop have it's own pll as parent.
Change-Id: Ia61e10918e14a69c053455018ddf0183ff15ea19
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
These clks will be enabed and disabled in pvtm driver.
Change-Id: I742a8c4ef5877486fb21c014f1e4ab27f72e468d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
if the dclk_vop0_div allow CLK_SET_RATE_PARENT for VPLL,
the dclk_vop1_div parent is not allowed in vpll.
Change-Id: I9973014e8ed2fcf1c351e3f62c00040677391ff7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
set pll sequence:
->set pll to slow mode or other plls
->set pll down
->set pll params
->set pll up
->wait pll lock status
->set pll to normal mode
To slove the system error:
rockchip_rk3399_wait_pll_lock: timeout waiting for pll to lock
rockchip_rk3399_pll_set_params: pll update unsucessful,
trying to restore old params
Change-Id: I62aecd9f292de5a3c7bcd8a87231785bf115159d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
If setting freq is not support in rockchip_pll_rate_table rk3399_pll_rates[],
It can set pll params by auto.
Change-Id: I5016cece64dca4c2efec18d552ee6be426f6b95a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The rk3399 hdmi phy is supplied by the vpll directly and needs to adapt
that frequency depending on the selected resolution on the hdmi output.
For the hdmi-phy the vpll frequency is supplied unchanged without
any dividers being present there.
The vpll also is one of the sources the general display clock of the
visual output processor (vop) and as it is somewhat special for
display operations possibly also the preferred pll source. Here a divider
is available between the pll-mux and the vop clock, so that this part
can adapt the resulting frequency if needed.
So to keep the vop clock in line with the target rate, set the newly
introduced CLK_KEEP_REQ_RATE flag for the dclk_vop clocks on rk3399.
(am from https://patchwork.kernel.org/patch/8993771/)
Change-Id: Iba9a179b764472f22d7531eb0c662dcd982433d4
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Given a hirarchy of clk1 -> [div] -> clk2, when the rate of clk1 gets
changed, clk2 changes as well as the divider stays the same. There may
be cases where a user of clk2 needs it at a specific rate, so clk2
needs to be readjusted for the changed rate of clk1.
So if a rate was requested for the clock, and its rate changed during
the underlying rate-change, with this change the clock framework now
tries to readjust the rate back to/near the requested one.
The whole process is protected by a new clock-flag to not force this
behaviour change onto every clock defined in the ccf.
(am from https://patchwork.kernel.org/patch/8993761/)
Change-Id: Ie2636710cb4e66815ee45b28ec86eeaaa47c55c7
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add usic node for rk3399 USB 2.0 EHCI controller
with usic phy.
Change-Id: Ibb4179ff1479816daa3b8455b0229f8a7a05bbdf
Signed-off-by: William Wu <william.wu@rock-chips.com>
mcu run at 97MHz to reduce lpddr4 scale frequency elapsed time
Change-Id: Ie2805eaf0d902c9531819217d05a86775d85f809
Signed-off-by: CanYang He <hcy@rock-chips.com>
