The Rockchip RK3308 has a gmac that is not fully compatible with any of the
other Rockchip gmacs.
This patch adds a compatible string for it.
Signed-off-by: Tobias Schramm <t.schramm@manjaro.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry-picked from 2cc8c910f5)
Change-Id: Ia9aaf7af18175b814a95252376fd299a6156f7d1
Signed-off-by: David Wu <david.wu@rock-chips.com>
Convert Rockchip dwmac controller dt-bindings to YAML.
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry-picked from b331b8ef86)
Change-Id: Ibb8e639fea8532260df3444e0deccf108affe70f
Add Rockchip DWMAC controllers, which are based on snps,dwmac.
Some of the SoCs require up to eight clocks, so maxItems
for clocks and clock-names need to be increased.
Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com>
Reviewed-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 517a882aa2)
Change-Id: Ie758eda2091dac5081bed325e2169a23ee3dc311
We need call wakeup_softirqd() for the softirqs not completed in irq_exit()
when CONFIG_RT_SOFTINT_OPTIMIZATION is not defined.
Fixes: 0578248bed ("ANDROID: softirq: defer softirq processing to ksoftirqd if CPU is busy with RT")
Change-Id: Id71afcd252ddc69d97ec5167845c602f3aaba3ac
Signed-off-by: Liang Chen <cl@rock-chips.com>
The driver can be compile tested with !CONFIG_OF making certain data
unused:
sound/soc/rockchip/rockchip_i2s.c:569:34: warning: ‘rockchip_i2s_match’ defined but not used [-Wunused-const-variable=]
sound/soc/rockchip/rockchip_pdm.c:463:34: warning: ‘rockchip_pdm_match’ defined but not used [-Wunused-const-variable=]
sound/soc/rockchip/rockchip_spdif.c:44:34: warning: ‘rk_spdif_match’ defined but not used [-Wunused-const-variable=]
Change-Id: Ib4533440ad912d28ee7828f3ae4644219fe1a0c6
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20201125164452.89239-12-krzk@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
(cherry picked from commit 56af27ad5f)
This reverts commit a3cab91402.
The mfd fusb302 driver previously used for Type-C port
of rockchip platforms, but it's not compatible with the
new Type-C framework, and there's a new fusb302 driver
in the driver usb typec framework, so remove this driver.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I1665d765bbd928541e7528ed6de86c378a02f16b
The CONFIG_FUSB_30X is used for legacy fusb302 driver
which has been deprecated, so remove it.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I722c8593be3a42f0b2434e284d3deb37e51429f1
Rockchip platforms don't support HS200 or HS400 at low speed, so
we must limit it.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: I40eb9f117fd83789b6ab7a16d44049e16786698b
As we mask our SDHCI controller as SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
host->max_clk is derived from core clock in the first place. Then
f_max works together with it.
If we adjust loader's core clk setting, such as 50MHz, we will get
50MHz for host->max_clk, because .get_max_clock() reads core clk
when probing driver. That will lead f_max be set to 50MHz as well,
no matter if max-frequency is set higher than 50MHz.
We can simple solve this problem by assigning core clk as 200MHz
in the first place and then let max-frequency property takes over
it.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Idb2fdb8f68881d0286d977dc3718b74c30d3bc67
RK3588 is an ARM DynamiQ architecture SoC, including 4 Cortex-A55 cores
and 4 Cortex-A76 cores.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: Id52349b39e28bc5a4fd3d0f17a712cd4c0797db8
arch/arm64/boot/dts/rockchip/rk3588s.dtsi:921.32-933.4: Warning (unit_address_format): /iommu@0xfdc38700: unit name should not have leading "0x"
arch/arm64/boot/dts/rockchip/rk3588s.dtsi:935.32-947.4: Warning (unit_address_format): /iommu@0xfdc48700: unit name should not have leading "0x"
Fixes: e1e1eabccd ("arm64: dts: rockchip: rk3588s: Add mmu nodes for video codecs")
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: If259e78e4454266bccbbb51ee808f59c0e62ace7
This adds USBDP combo PHY1 related nodes for RK3588 SoCs.
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Change-Id: I2afb41c8f57ab49c13ecee110a78c9b7f011e3fe
The rk3588s has three independent USB 2.0 PHYs. And
each PHY has one port. The connection between the PHYs
and the controlles is as follows：
USB2 PHY0 to USB3 OTG0
USB2 PHY2 to USB2 HOST0
USB2 PHY3 to USB2 HOST1
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I300dcf4fdf6e4688a7e1598e9e2f4bb17d48acbc
Most of rockchip platforms support power domain for dwc3.
Allow the pm runtime to manage the power domain for dwc3
in the dwc3 runtime PM routine.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I49e3fa207db8aea0355a797b69c9c8a791d2eaa3
If the dwc3 core is programmed to operate in usb 2.0 only
mode, and no usb 3.0 phy, then it needs to set the bit
DEV_FORCE_20_CLK_FOR_30_CLK of GUCTL1 to make the internal
2.0(utmi/ulpi) clock to be routed as the 3.0 (pipe) clock.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Change-Id: I217a380815c21903c1090bd003c1d8ba2fadbe7c
