Fixes: d7ad116fb3 ("drm/rockchip: analogix_dp: Add support for rk3568")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I8cef87e13dd7c03baac730523c8f4b98d1a043f2
use actual pixel or dot clock in the hardware to calc the
timings and lane rate if dclk can not be applied accurately.
Change-Id: I6c0bcaca35cb945a58cc50005b23c6c772c9a082
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Move udma related config and start operation to master place and expose
as a hook, udma trx obj just call the hook.
Change-Id: If410280629eafa9d8829ac89a8cef6e931b37c3c
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Some resolution(eg: 4096x2049) can't display when AFBC auto gating
enabled.
Change-Id: Iadd2db1e600c7c0bae10ead0851476f2cf3bbe34
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
This is needed for rk3566 rk817 tablet.
Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: I4180aae4e40677f456ee10aff8760288a1fd79bc
1. Add clks enable and disable control.
2. Do PCIe/USB3/SATA phy init in their own helper.
3. Select ref clk according to ref clk rate for RK3568
4. Set SSC clk rate and SSC derection for the USB3 of RK3568.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Change-Id: If2959147cfe9f799c88c31ef7cefbccc872a3bf4
ppll is for combophy refclk to lock, and it should support
25M/100M. So we need to increase it to 200MHz.
Change-Id: I224a221296ed074a60354d65e7c678de4f7f7120
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
1. set dr_mode to otg for usbdrd_dwc3.
2. remove usbhost30 and u2phy0_host, these are unused.
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Change-Id: Ia93df0660552bb54211252f4c35d72d8a1ef7934
Vop2 can't share the same scale factor calculate
algorithm with rk3399 on some situation, even they
use the same scale algorithm.
Change-Id: I90dd39b2482d39d56ee94046830facc4d20f5cb2
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
There is a risk of access failure, if pclk
is enabled without enabling hclk in rk3568.
Change-Id: I02c2a0d8ad6c0d2c6649ee16ab50dda0da542aac
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
regulator_suspend_enable(), regulator_suspend_disable() and
regulator_set_suspend_voltage() are all exported members of the
API, but are all missing prototypes.
Fixes the following W=1 warning(s):
drivers/regulator/core.c:3805:5: warning: no previous prototype for ‘regulator_suspend_enable’ [-Wmissing-prototypes]
3805 | int regulator_suspend_enable(struct regulator_dev *rdev,
| ^~~~~~~~~~~~~~~~~~~~~~~~
drivers/regulator/core.c:3812:5: warning: no previous prototype for ‘regulator_suspend_disable’ [-Wmissing-prototypes]
3812 | int regulator_suspend_disable(struct regulator_dev *rdev,
| ^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/regulator/core.c:3851:5: warning: no previous prototype for ‘regulator_set_suspend_voltage’ [-Wmissing-prototypes]
3851 | int regulator_set_suspend_voltage(struct regulator *regulator, int min_uV,
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Change-Id: I1ccdd34e5a7c42976472a00b4b17547bd741509e
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Link: https://lore.kernel.org/r/20200625163614.4001403-2-lee.jones@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit da6690767c)
According to the test on HDMI, when vop do csc(rgb2yuv444),
it need a rb_swap to show right color. But yuv420 don't
need to do so.
Change-Id: I16c7530b015bd67a584cf39304df9b9f5b0d7a29
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
The usb phy could update the state of the EXTCON_CHG_USB_DCP duly, so
that we can change the current limit to maximum within the USB dedicated
charging port.
Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Change-Id: I32f0361a2f0153424627bef0bd75c3b93e51ec03
It turns out to be that RK356X platforms is only support to work
reliably under HS200 mode. We now officially remove HS400
support from datasheet, as well as dts.
Change-Id: Icb7cff46a6d757d1615360c04f4b20b3a5bdd6d2
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
