init temp_last with a more suitable value. also we eliminate
the steady state error by ajusting the temp calc fomular.
extra useful log is added to mark tsadc is probed successfully.
Change-Id: If88031c10646437fa7b5152c70aeaebf93e4df05
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
the mux_spdif_8ch_p is composed of spdif_8ch_src not spdif_8ch_pre
Change-Id: I7dd40e35078b2d012af2c777de763d14e93c3d4e
Signed-off-by: Xinhuang Li <buluess.li@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
From Rockchips fractional divider usage, some clocks can be generated
by fractional divider, but the input clock frequency of fractional
divider should be less than a specified value.
Change-Id: Ifd6c5f6a24a64021f990506e8657cd925f9b96f9
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
If change parent to alternate parent and the old parent clock speed is less
than the clock speed of the alternate parent, add dividers first and then
select alternate parent.
If change parent to primary parent, select primary parent first and then
remove dividers.
Change-Id: Ib82de9a936effe5c885639799f3bb5629dc89f8d
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Tsadc has a tshut pin which is designed to reset the pmic or soc,
when the temperature inside soc is too high. we should switch off
the tshut function and change the pin to gpio function in reboot
process, eg, software reset. If not, the tsadc module will WRONGLY
pull high the tshut pin during its reset process and then WRONGLY
reset the pmic or soc, which incurred a hardware reset. The hardware
reset will reset everything inside soc, even includes the power on
reason flag, which is set by software before reboot process.
we also change over-temperature protection mode to cru mode,
since the tshut pin have be changed to gpio function.
Change-Id: Iac3dacf55a4b5536fccd2eb05a6a9e6923a082c0
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Prevent the system from entering suspend when usb cable is connecetd.
Change-Id: I50c4a09d9142ebeb2d4e2a0ab2df59f98ef99737
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch adds bypass uart cfgs for rk1808 USB 3.0 OTG
port. In addition, please note that it needs to set the
uart2 rx/tx io selection in the reg "BUS_GRF_IOFUNC_CON0"
bit 15:14.
Change-Id: I77ea461be299c0454f5caee1349110b6f2714c30
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
RK1808 SoC has an usb 2.0 comb phy with one otg-port and one
host-port. This patch adds port configurations for them.
Change-Id: Id4d117929ec0e327c8f2cc1a06d4caaa2d584f06
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
We find an usb phy 480MHz clk prepare fail issue on PX30/RK3326
platforms with RK819 PMIC. On PX30/RK3326 platforms, we set the
usb480m clk to critical because GPU 480M is from usb480m and the
source clocks should be always on. And the usb phy 480MHz clk is
parent of usb480m clk, so the clk framework will prepare the usb
phy 480MHz clk when register it.
This logic works well if the usb phy probe only once. But if the
usb phy needs to probe twice or more because of some reasons (e.g.
fail to get vbus regulator from RK819), the usb phy 480MHz clk will
be unregistered and registered again, however, the clk framework
doesn't prepare the usb phy 480MHz clk except the first time register
operation. So we move the 480MHz clk register to the end of probe,
and make sure only register it once.
Change-Id: If69378b49035746a7c0107c6a363c4d91dfc15e5
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Bin Yang <yangbin@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch adds rk3368 otg-port phy configurations.
But actually, we don't use the otg phy configurations
for the time being, because we use dwc_otg_310 driver
for rk3368 otg controller, and this driver doesn't use
generic phy. This patch is useful if we switch to dwc2
driver for rk3368 otg in the feature.
Change-Id: Ibed3fde4ef64ad25e933ac4560f956b7c9f5c476
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Because USB OTG id irq is disabled during system suspend
and enabled after resume, so the usb2 phy doesn't notice
any id status change upon resume. It may cause two issues:
1. Plug in OTG cable and USB device when system enter
suspend, it will fail to detect the OTG cable and
USB device after resume.
2. Plug out OTG cable and USB device when system enter
suspend, and then connect USB to PC or USB charger
after resume, it will fail to detect USB charge type.
This patch restores the OTG id status before enter suspend，
and check the id status upon resume, and set the extcon
state and vbus if id status has changed.
Change-Id: Iaca14841cc287e7d82e1cffd64ff18bba86d3ba4
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The controller will be reinit when suspend and resume in device
mode if not connect to PC. And the U2PHY must be keep in power
on state during the init process. But The 'otg_sm_work' may be
schedule immediately and power off the U2PHY if system suspend
and resume between the delay time of schedule 'otg_sm_work', so
it will result in the error when init controller as below:
dwc2_core_reset() HANG! Soft Reset GRSTCTL=80000001
So flush the otg work in exit function to finish power control
of U2PHY.
Change-Id: I79c4b6a877196abd2f2201b2f984c9ea22e48fec
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patches fixes comparison between signed and unsigned values.
Change-Id: Ie417fdb8092463890a67bce7efa11f3ef20d5871
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch fix the following clang warning:
[clang]drivers/phy/rockchip/phy-rockchip-inno-usb2.c:1255:3:
warning: Value stored to 'delay' is never read
Change-Id: I8c70975e1bc2b24a78d0934ccefc9d67fe3a5da9
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Reduce the otg schedule delay time from 6s to 1s to do
the first time usb charger detection earlier when power
on system with usb cable connect to PC USB. Because the
usb connection willed be disconnectted during usb charger
detection.
And the patch also makes the phy detect the usb disconnetion
more quickly after usb cable plug out.
Change-Id: I9b55317ab3592f517fdf590fea85c4ed403bbd8d
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Open pre-emphasize in non-chirp state for rk3228 USB
PHY0 otg port to increase HS slew rate.
Change-Id: Ia565746286a750a251619a83cbbead99c0ddecbd
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Make u2phy enter low power mode when suspend. If config the DT of
u2phy port with "rockchip,low-power-mode" property, the port will
be config to lower power state when suspend.
Bvalid irq and linestate irq will be disabled in this mode.
Change-Id: Ie7d40a9a181b0622b1f8d062a741661548cabd59
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Open pre-emphasize in non-chirp state for rk3308 and
rk3328 usb otg and host ports to increase HS slew rate.
Change-Id: I16435d67b9994cef0fd5e6edbae00c41cc02c48b
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This change adds usb-phy support for rk3308 SoC and amend related
phy Documentation.
Change-Id: I953af94fb4d55d79ae1cba624a04fb4b84e019f6
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Due to usb-phy tuning framework is not added in UPSTREAM codes, so
rk3328 tuning is striped in mainline, this commit make a supplement.
Change-Id: Id8103d65951515b9b21baab14f7125420cea78eb
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
This patch uses a fixed-regulator instead of GPIO pin for
usb vbus power. It doesn't fix any issue, but it makes more
sense to convert the GPIO code into a fixed-regulator.
Change-Id: I7196a9cd592dbb3fab3ef8b9e99babc613a42869
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
In current code, the pre-emphasize in eop state and chirp state are
disabled only if we add “rockchip,u2phy-tuning” property in RK3399 dts,
But we find that if we enable the pre-emphasize of sop/eop/chirp state
for rk3399 by default, it will cause usb2 compliance test item - EL_8
and EL_9 failure, so disable the pre-emphasize of sop/eop/chirp state
by default. And this can also help to avoid mis-trigger the disconnect
detection or high-speed handshake failure.
Change-Id: I5ceac9c88de4cdae5af904e973124c194f7718f6
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The usb2 phy driver will power off phy if it detects
usb connecting with usb charger. And then it schedule
a delayed work to check the connection state until the
usb disconnect from usb charger.
On rockchip platform, the usb2 controller utmi clk and
480MHz clk come from usb2 phy, so if we power off the
usb2 phy, the usb2 controller should not be accessed.
However, it's difficult to synchronize the phy state
between the usb2 phy driver and usb2 controller. We
find one synchronization problem in the following
case:
1. Test on rk312x platform;
2. Connect otg port with usb charger, then do suspend/
resume stress test.
3. We will find the following error log, and then the
usb controller work abnormally.
dwc2 10180000.usb: resuming usb gadget configfs-gadget
dwc2 10180000.usb: dwc2_core_reset() HANG! Soft Reset GRSTCTL=80000001
This because in dwc2 driver, it will do dwc2 core reset
during resume, although it also power on usb2 phy before
do core reset, but the otg_sm_work in the usb2 phy driver
may power off the usb2 phy again asynchronously, this will
cause dwc2 core reset failure.
So we should not power off the usb2 phy if connect to
usb charger, this patch will increase the usb2 phy power
consumption in runtime, but it don't affect the power
consumption in system standby mode, because the usb
controller can power off phy by itself during suspend.
Change-Id: I3b05c06988b7939ebf949ced34b9a6bb37ffa42a
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Turn off differential receiver in suspend mode to save power
Change-Id: Idd9b4c2d7d9d78915c94946ced99737683a2ce91
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
When detect the usb peripheral disconnect from PC usb
host port or usb charger, we need to reinit the charge
state immediately, then it can do usb battery charge
detect work to get correct charge type if usb re-plug
in again in a short time.
Change-Id: I187f1d23a11b00f57e0a3699b6174cd7a59be3f1
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Most of rockchip SoCs USB 2.0 DP/DM can be bypassed to UART,
it's useful for those platforms without UART interface to
print log via USB interface.
For the time being, we just support for rk312x and rk3399 in
this driver. And we will support for more SoCs in the feature.
With this patch, the user still can't use this bypass function.
It needs to add the property "rockchip,bypass-uart" in the DT
as following:
u2phy0_otg: otg-port {
...
rockchip,bypass-uart;
...
};
And it also needs a special USB cable integrated with an USB
to UART chip.
Note: this function can only be used in debug stage.
Change-Id: Icdab516ff7b327f4a98c3b24bbaf953a605f5278
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The rk312x use different config data which incluce control
register address and value. The patch add config data of
rk312x and match table to support rk3128.
Change-Id: Idd9a5c885cf5e291517e56232e77066eb5d97138
Signed-off-by: Meng Dongyang <daniel.meng@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Commit 4f519feed0 ("phy: rockchip-inno-usb2: delay suspending
phy if plug out device"), introduced the following issue:
BUG: sleeping function called from invalid context at kernel/workqueue.c:2717
in_atomic(): 1, irqs_disabled(): 128, pid: 4, name: kworker/0:0
INFO: lockdep is turned off.
irq event stamp: 19674
hardirqs last enabled at (19673): [<ffffff8008cd8818>] _raw_spin_unlock_irqrestore+0x40/0x70
hardirqs last disabled at (19674): [<ffffff8008cd8690>] _raw_spin_lock_irq+0x1c/0x60
softirqs last enabled at (19664): [<ffffff80088dd1c0>] dw_mci_request+0xe0/0xf0
softirqs last disabled at (19660): [<ffffff80088dd140>] dw_mci_request+0x60/0xf0
CPU: 0 PID: 4 Comm: kworker/0:0 Not tainted 4.4.83 #69
Hardware name: Rockchip RK3399 Evaluation Board v3 (Android) (DT)
Workqueue: fusb302_wq fusb302_work_func
Call trace:
[<ffffff8008089f78>] dump_backtrace+0x0/0x1cc
[<ffffff800808a158>] show_stack+0x14/0x1c
[<ffffff80083ca33c>] dump_stack+0xb8/0xf4
[<ffffff80080cec40>] ___might_sleep+0x1b8/0x1c8
[<ffffff80080cecc0>] __might_sleep+0x70/0x80
[<ffffff80080becbc>] flush_work+0x74/0x270
[<ffffff80080bf09c>] __cancel_work_timer+0x12c/0x1bc
[<ffffff80080bf154>] cancel_delayed_work_sync+0x10/0x18
[<ffffff80083f9de8>] rockchip_otg_event+0x18/0x3c
[<ffffff80080c6380>] notifier_call_chain+0x54/0x88
[<ffffff80080c63dc>] raw_notifier_call_chain+0x14/0x1c
[<ffffff80089a5354>] extcon_sync+0x74/0x1c4
[<ffffff80085ab980>] platform_fusb_notify+0x184/0x204
[<ffffff80085ac4ac>] set_state_unattached+0x5c/0x90
[<ffffff80085ac85c>] fusb302_work_func+0x288/0x1904
[<ffffff80080bdfa4>] process_one_work+0x354/0x6d0
[<ffffff80080bf4a4>] worker_thread+0x2f8/0x414
[<ffffff80080c4e58>] kthread+0xf0/0xf8
[<ffffff80080828d0>] ret_from_fork+0x10/0x40
Actually, we don't need to cancel the otg_sm_work in the
event EXTCON_USB_HOST notifier_call. So just remove the
cancel_delayed_work_sync() in the rockchip_otg_event().
With this patch, we may get USB BC1.2 detection error
if plug in USB peripheral/host cable alternately and
quickly. So we need to reinit chg_state and chg_type
if OTG host cable plug in.
Change-Id: I349d59de3188d39707c527acb858a7be20a999ac
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
rk3399 Type-C1 USB 2.0 PHY supports USB BC1.2. This patch
adds registers configuration for Type-C1 USB BC1.2.
With this patch, and set dr_mode of Type-C1 USB to "otg" or
"peripheral" in the DTS, then the Type-C1 USB can detect USB
battery charger.
Change-Id: I2f07ae675cc6066db46e428e6e27045b911a0773
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Let us put phy-port into suspend mode at initialization time for
saving power consumption, and usb controller will resume it during
probe time if needed.
Change-Id: Id3a66af8ff17612d54fbc80db087bf67eaee7726
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
The otg_sm_work will suspend the usb2 phy immediately
if it detects disconnection from host. However, the usb2
controller(e.g. DWC2) may need to reinit registers and
reset usb core after usb disconnect, and it needs to
keep the usb2 phy stay in power on state to get utmi clk
for these usb controller operation. We don't have a good
synchronization mechanism to operate usb2 phy between
usb2 phy driver and usb2 controller driver, so we delay
4s to suspend phy if detect otg device disconnect from
host, this can make sure that usb2 controller completes
reinitialization before suspend usb2 phy.
Change-Id: I79288b8c7b141bb16e6d96d80cfee75f7558d2c0
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
