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Author SHA1 Message Date
Simon Xue
d66101a3fe iio: adc: rockchip_saradc: add rk3562 
Change-Id: Id4d47ff54d194a4312487f4a07698d3cd6405112
Signed-off-by: Simon Xue <xxm@rock-chips.com>
 2023-02-02 19:02:08 +08:00
Chandler Chen
d76a85467f video: rockchip: mpp: link mode support for rk3562 
Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
Change-Id: I8fe2d951554ed2f178c8509aabe166427ccaf096
 2023-02-02 19:02:08 +08:00
Chandler Chen
319dab507b video: rockchip: mpp: rkvenc2: match rk3562 encoder compatible 
Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
Change-Id: I575b599d52825aa6d91cd562aed16d664efe765e
 2023-02-02 19:02:08 +08:00
Jon Lin
4f0c9ccc79 pcie: rockchip: dw: Support rk3562 
rk_pcie_of_data is the same with RK3528.

Change-Id: I161dfd939ff72e72a61588ff5ed953d2b600f48d
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 2023-02-02 19:02:08 +08:00
Jon Lin
0cdb526c1f phy: rockchip-naneng-combo: Support rk3562 
Change-Id: I4da12613bb01c477f8fca9c38c516f5dab0851d9
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2023-02-02 19:02:08 +08:00
Frank Wang
63f30f7541 phy: rockchip: inno-usb2: add usb2 phy support for rk3562 
RK3652 has one USB2.0 PHY with two ports, the OTG port support OTG
and BC1.2, the SoC provide USB GRF and APB to access the registers.

This adds vbus detection function control and make the below tuning
to enhance the usb2-phy SQ for RK3562 SoC.
 - enable pre-emphasis during non-chirp phase
 - set HS eye height to 425mv
 - turn off differential receiver by default to save power

Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: If93c3a072be4c532aa823cf3cd9f05fe9414f727
 2023-02-02 19:02:08 +08:00
Zhang Yubing
36c9d7fd8f drm/rockchip: lvds: add support rk3562 
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I95a42245599c2440b6405fcfd048e9b32b1636c9
 2023-02-02 19:02:08 +08:00
Sandy Huang
a2bb42f791 drm/rockchip: rgb: add support rk3562 
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Iefbb7f45bbafcd5bbfb6840d0968c9b6aef6b709
 2023-02-02 19:02:08 +08:00
Sandy Huang
636cad1344 drm/rockchip: vop3: fix init value error for rk3562 vp1 
This two bit is reserved for hdr and it is enabled by default,
is less this commit, vp1 will display black screen always.

Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I38862d187a1e26322c3e8930b615c4eb9d5f4ef8
 2023-02-02 19:02:08 +08:00
Sandy Huang
36e5e07f5c drm/rockchip: vop3: add support rk3562 
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I3e7b430331640590591b7828672c756cee5fca92
 2023-02-02 19:02:07 +08:00
Guochun Huang
989ea6103a drm/rockchip: dsi: Add support for rk3562 
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I7ab1d79d069be85bb34060dd4cfc60464b7ded55
 2023-02-02 19:02:07 +08:00
Shaohan Yao
dfdb9d1b2f thermal: rockchip: Support the rk3562 SoC in thermal driver 
There are one Temperature Sensor on rk3562, channel 0 is for chip.

Signed-off-by: Shaohan Yao <shaohan.yao@rock-chips.com>
Change-Id: Ided46b86470bb9cd506206bb4880ca024c0ec5cf
 2023-02-02 19:02:07 +08:00
Finley Xiao
86921d7d83 nvmem: rockchip-otp: Add support for rk3562 
This adds the necessary data for handling otp on the rk3562.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I5083f7881146b18532bcee170ef78274b31ee4be
 2023-02-02 19:02:07 +08:00
Jason Zhu
2b098cb6c8 arm64: dts: rockchip: rk3562-evb: Add spdif and pdm support 
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: Ibff940d2007fe5c6316879fa38819d598e674325
 2023-02-02 19:02:07 +08:00
Damon Ding
21c141e2dc arm64: dts: rockchip: rk3562-evb: add sii902x bt1120/bt656 to hdmi board 
vp0->mipi dsi
vp1->bt1120/bt656->hdmi

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Id0c7be8a3532d116997219461fd7722e2aae740a
 2023-02-02 19:02:07 +08:00
Steven Liu
4663ac10bc arm64: dts: rockchip: Add RK3562 linux amp dts 
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: I896bb705fbabfe032879bd03d21964f220141e76
 2023-02-02 19:02:07 +08:00
Binyuan Lan
6125424e87 arm64: dts: rockchip: add rk3562-rk817-tablet-v10 board devicetree 
Change-Id: If251014d87c787978da5541b85e0121b89555296
Signed-off-by: Binyuan Lan <lby@rock-chips.com>
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
 2023-02-02 19:02:07 +08:00
Finley Xiao
ed8b64e07c arm64: dts: rockchip: Add RK3562 test1 and test2 board devicetree 
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I1884bb4385a739b212f924f9996fe250ca0e8ffd
 2023-02-02 19:02:07 +08:00
Zhang Yubing
1a5b510ed7 arm64: dts: rockchip: Add RK3562 EVB1 LP4X V10 LVDS Board 
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: I08e08546dec92b62a15b4e4cd3434a00df72eb6f
 2023-02-02 19:02:07 +08:00
Finley Xiao
4aa12ffbf8 arm64: dts: rockchip: Add RK3562 iotest board devicetree 
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Signed-off-by: Jake Wu <jake.wu@rock-chips.com>
Change-Id: I1de47c3fc46e1e95c9ad77efa2b697edffdd5c6d
 2023-02-02 19:02:07 +08:00
Finley Xiao
2df94e8259 arm64: dts: rockchip: Add RK3562 evaluation board devicetree 
evb1: LPDDR4/LPDDR4X + RK817 + ECM MIC
evb2: DDR4 + RK809 + RTC IC with external BAT + SPI Flash + MEMS MIC

The rk3562-evb1 and rk3562-evb2 force the maximum-speed of
usb dwc3 controller to high-speed, it needs the following
two properties to fix usb compatibility issues.

1. Set "snps,dis_u2_susphy_quirk" to disable dwc3 controller
   suspend phy automatically. And the usb phy driver can
   manage phy suspend/normal mode by itself.

2. Set "snps,usb2-lpm-disable" to disable usb2 lpm for dwc3
   xhci controller. It can fix some usb disks with lpm broken
   issue.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Li Huang <putin.li@rock-chips.com>
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Signed-off-by: Jake Wu <jake.wu@rock-chips.com>
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Binyuan Lan <lby@rock-chips.com>
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Felix Zeng <felix.zeng@rock-chips.com>
Signed-off-by: Wangqiang Guo <kay.guo@rock-chips.com>
Change-Id: I066b6daa6d0f36ff0b28564f07f4d371c2796fd6
 2023-02-02 19:02:07 +08:00
Finley Xiao
8d580cfd19 arm64: dts: rockchip: add core dtsi for RK3562 Soc 
RK3562 is a Soc from Rockchip, which embedded with quad
ARM Cortex-A53.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Signed-off-by: Yu Qiaowei <cerf.yu@rock-chips.com>
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
Signed-off-by: Xuhui Lin <xuhui.lin@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Li Huang <putin.li@rock-chips.com>
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Signed-off-by: David Wu <david.wu@rock-chips.com>
Signed-off-by: Cai YiWei <cyw@rock-chips.com>
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Signed-off-by: Shaohan Yao <shaohan.yao@rock-chips.com>
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Signed-off-by: Chandler Chen <chandler.chen@rock-chips.com>
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Signed-off-by: Felix Zeng <felix.zeng@rock-chips.com>
Signed-off-by: Zefa Chen <zefa.chen@rock-chips.com>
Signed-off-by: Jake Wu <jake.wu@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Liang Chen <cl@rock-chips.com>
Change-Id: I0d8d52eee06b7e962434510fbfb214c01d25ef36
 2023-02-02 18:54:49 +08:00
Finley Xiao
402eeba39b soc: rockchip: power-domain: add power domain support for rk3562 
This driver is modified to support RK3562 SoC.
Add support to ungate clk.
Add support to shut down memory for rk3562.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ideeaf378b0548a9a32e05345f56a6d6bfb037a20
 2023-02-02 18:54:49 +08:00
Finley Xiao
13dc7de2e4 dt-bindings: add power-domain header for RK3562 SoC 
According to a description from TRM, add all the power domains.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ia188dad23c884521775f9e608203d1281b093a39
 2023-02-02 18:54:49 +08:00
Finley Xiao
a621b1189c clk: rockchip: Add clock controller for the RK3562 
Add the clock tree definition for the new RK3562 SoC.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ia96ad61555537333a8ac54158360e1d23d971135
 2023-02-02 18:54:49 +08:00
Finley Xiao
14d8aa4a04 clk: rockchip: add dt-binding header for rk3562 
Add the dt-bindings header for the rk3562, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rk3562.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Liang Chen <cl@rock-chips.com>
Change-Id: I25c4b2b8276f7d371ae861fdd24bd98fcf7c1629
 2023-02-02 18:54:49 +08:00
Steven Liu
1d9713df4e pinctrl: rockchip: add rk3562 support 
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Change-Id: Ifaa8c80bf109ed6b710e4d1ccb3e2bf379bc0299
 2023-02-02 18:54:49 +08:00
Finley Xiao
bacbf200df arm64: configs: rockchip_defconfig: enable CPU_RK3562 
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I374fb618f898c3bbe6ab9baadc1248fa10f371a1
 2023-02-02 18:54:49 +08:00
Finley Xiao
19566d9146 soc: rockchip: Adds CPU_RK3562 config 
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I6b2911bb567c794be5c1b77fbd4632006b08de7a
 2023-02-02 18:54:49 +08:00
Shawn Lin
9fbb9ccaf7 mmc: sdhci-of-dwcmshc: Sync code with upstream as possible 
To make backport and upstream work easier. After this patch,
we just need to focus some rk specific additional code.

Sync to upstream commit a0753ef66c ("mmc: sdhci-of-dwcmshc: Re-enable support for the BlueField-3 SoC").

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ie3b76ea2848ac3570bb9bc0be09c6f6a67685658
 2023-02-02 16:54:00 +08:00
Shawn Lin
8e4a5fef5b arm64: dts: rockchip: rk3568: Rename sdhci compatible property 
Since we modify the sdhci driver to match upstream, so the compatible
property should be adjust to match it.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ia768d530047db95c29d5740ed5b039e7d92428cc
 2023-02-02 16:20:23 +08:00
Huang zhibao
a3e576bb9d arm64: dts: rockchip: rk3528-evb: remove firmware node 
Signed-off-by: Huang zhibao <hzb@rock-chips.com>
Change-Id: Ie5542723077158e1c17f019bd6a8d46eafe3c1bf
 2023-02-02 16:19:33 +08:00
Jianqun Xu
979b9e6c84 media: rockchip: subdev-itf: remove empty runtime suspend/resume 
drivers/media/platform/rockchip/cif/subdev-itf.c:1172:12: warning: 'sditf_runtime_resume' defined but not used [-Wunused-function]
error, forbidden warning:subdev-itf.c:1172
 1172 | static int sditf_runtime_resume(struct device *dev)
      |            ^~~~~~~~~~~~~~~~~~~~
drivers/media/platform/rockchip/cif/subdev-itf.c:1167:12: warning: 'sditf_runtime_suspend' defined but not used [-Wunused-function]
error, forbidden warning:subdev-itf.c:1167
 1167 | static int sditf_runtime_suspend(struct device *dev)
      |            ^~~~~~~~~~~~~~~~~~~~~

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I537818f182741704e55f0bb59c623e1118bf5838
 2023-02-02 14:17:45 +08:00
Tao Huang
1d40129dd7 crypto: rockchip: Use fallthrough pseudo-keyword 
Replace /* fall through */ comment with pseudo-keyword macro fallthrough[1]

[1] https://www.kernel.org/doc/html/latest/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through

Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Change-Id: I717c6a69079e0fa502a9fd11665bb47e51893ff3
 2023-02-02 10:10:37 +08:00
William Wu
f658eb3ee6 Revert "usb: gadget: add transfer_type in struct usb_ep for rockchip" 
This reverts commit bcf7606d61.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Ic493a5f24217b728925ec71a5e47b0a3534de764
 2023-02-02 10:06:36 +08:00
William Wu
da52789497 Revert "usb: gadget: transfer_type depends on CONFIG_NO_GKI" 
This reverts commit 866525fd9f.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: Iba893b9036a01bcdc981311a9846b2375e167c02
 2023-02-02 10:06:36 +08:00
William Wu
023c6f447c usb: gadget: f_uac1: Fix ep addr matching when handle sample rate 
The f_uac1 driver uses the fixed address matching for EP-IN
and EP-OUT (0x82 for EP-IN and 0x01 for EP-OUT) when set/get
sample rate. It has limitation that can only support uac1 func
with EP2-IN and EP1-OUT to set/get sample rate. This patch use
the in_ep->address and out_ep->address instead of the fixed
addresses.

Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I85f4da663535b4e832e52b42bc1a7d57b85270ee
 2023-02-02 10:03:12 +08:00
Jianqun Xu
f573762ff5 soc: rockchip: rk_fiq_debugger fix the 'cpu' to unsigned long 
Change-Id: I5f432f86226f30df8a565407544ee46e7129e045
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
 2023-02-02 09:52:12 +08:00
Wang Panzhenzhuan
486a9a69ed media: i2c: cn3927v: fix suspend cause i2c error issue 
1. fix suspend cause i2c error issue.
2. use v4l2_dbg replace dev_dbg for dynamic print debug info.

Signed-off-by: Wang Panzhenzhuan <randy.wang@rock-chips.com>
Change-Id: I6445fbc6602d5b1ca3f7d8ef24764c468c63256f
 2023-02-01 18:11:03 +08:00
William Wu
7a4ae778bd usb: gadget: uvc: fix uvc state for bulk transfer 
Set uvc state to UVC_STATE_STREAMING when stream on uvc
for both isoc and bulk transfer, then it can schedule
video pump work in uvc_v4l2_qbuf.

Fixes: c15a7cecb8 ("usb: gadget: uvc: support streaming bulk transfer")
Change-Id: Ie6fab6529cd83d59b34c6dd0028d6ad5b5eed010
Signed-off-by: William Wu <william.wu@rock-chips.com>
 2023-02-01 18:10:06 +08:00
Sugar Zhang
6c4dd79500 ASoC: rockchip: vad: Use snd_soc_find_dai_with_mutex 
Ref: commit 20d9fdee72 ("ASoC: soc-core: add snd_soc_find_dai_with_mutex()")

This patch fix potential WARNING when config enable CONFIG_LOCKDEP

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I5f830cfcd68a7c819f6613786b78bc6d1519fc9e
 2023-02-01 18:05:09 +08:00
Sugar Zhang
b8bbd0d907 ASoC: rockchip: multi-dais: Use snd_soc_find_dai_with_mutex 
Ref: commit 20d9fdee72 ("ASoC: soc-core: add snd_soc_find_dai_with_mutex()")

This patch fix WARNING when config enable CONFIG_LOCKDEP:

WARNING: CPU: 2 PID: 1 at sound/soc/soc-core.c:816 snd_soc_find_dai+0x120/0x128
Modules linked in:
CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.10.66 #121
pstate: 60c00009 (nZCv daif +PAN +UAO -TCO BTYPE=--)
pc : snd_soc_find_dai+0x120/0x128
lr : snd_soc_find_dai+0x40/0x128
sp : ffffffc0130eb910
x29: ffffffc0130eb910 x28: 0000000000000000
x27: ffffff80eefdeda0 x26: 0000000000000002
x25: 0000000000000002 x24: ffffff800c20a590
x23: ffffff80ef06a6e8 x22: ffffff800c20a480
x21: ffffff800c1ab680 x20: ffffff80048f8800
x19: ffffffc0130eb970 x18: ffffffc0130e5098
x17: 0000000000000001 x16: ffffff8003d18000
x15: ffffffc012f86000 x14: ffffffc0125e6ce8
x13: 00000000ffffffff x12: ffffffc0129b8d68
x11: 0000000100000003 x10: 00000000ffffffff
x9 : 0000000000000000 x8 : ffffffc0dcdb3000
x7 : ffffffc010640fc0 x6 : ffffff8003d18990
x5 : 0000000000000000 x4 : 0000000000000001
x3 : e358acf3a5519911 x2 : 0000000000000001
x1 : ffffffc01246bf58 x0 : 0000000000000000
Call trace:
 snd_soc_find_dai+0x120/0x128
 rockchip_mdais_probe+0x1cc/0x730
 platform_drv_probe+0x9c/0xc4
 really_probe+0x20c/0x51c
 driver_probe_device+0x80/0xc0
 device_driver_attach+0x7c/0xc0
 __driver_attach+0xcc/0x158
 bus_for_each_dev+0x80/0xd0
 driver_attach+0x28/0x38
 bus_add_driver+0x108/0x1e8
 driver_register+0x7c/0x118
 __platform_driver_register+0x48/0x58
 rockchip_mdais_driver_init+0x20/0x30
 do_one_initcall+0x9c/0x190
 do_initcall_level+0xa4/0xc8
 do_initcalls+0x58/0x9c
 do_basic_setup+0x28/0x38
 kernel_init_freeable+0x9c/0xf8
 kernel_init+0x18/0x190
 ret_from_fork+0x10/0x30

Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I16b9642fc1022389e099de0fb98b31201eafe0a1
 2023-02-01 18:04:49 +08:00
Wu Liangqing
ffbaf9faee arm64: dts: rockchip: remove androidboot bootargs for px30/rk3399 boards 
Change-Id: I7a04b215fba6d6967bb241f1d07f0199612ccc9c
Signed-off-by: Wu Liangqing <wlq@rock-chips.com>
 2023-02-01 17:18:39 +08:00
Damon Ding
cc49e88e80 drm/bridge: sii902x: add FIELD2_OFST config 
The reg FIELD2_OFST should be half the number of pixel/line
in interlace mode.

Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I3b0de9199768d965a945bf5db5a0902f2103e30e
 2023-02-01 16:38:06 +08:00
shengfei Xu
83274139e2 arm64: dts: rockchip: rk3588-rk806-dual: fix nldo1/nldo2/nldo3 supply 
The input supply is always-on, so this mistake doesn't affect
whether the supply is actually enabled correctly.

Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: Ie6411c6fdcf4865290ba725d8203334f1bf8ad35
 2023-02-01 16:12:24 +08:00
Wyon Bi
c4cc8de208 drm/rockchip: dw-dp: Fix a typo 
Fixes: 7d048d6dac ("drm/rockchip: dw-dp: Add HDCP function support")
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Change-Id: I5882ae3d54340c7e25cf25b491ed3e6006f01c6c
 2023-02-01 07:46:15 +00:00
Jianqun Xu
c36c85bec0 video: rockchip: dvbm: fix a compile warning 
drivers/video/rockchip/dvbm/rockchip_dvbm.c: In function 'rk_dvbm_setup_iobuf':
./include/linux/kern_levels.h:5:18: warning: format '%x' expects argument of type 'unsigned int', but argument 2 has type 'dma_addr_t' {aka 'long long unsigned int'} [-Wformat=]

Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: Ia18c7da7ea47e168741f76365eedc6b9e630e527
 2023-02-01 15:17:05 +08:00
Jon Lin
25f0206a15 spi: rockchip: Add print information in case of spi exception 
Change-Id: I3c512486ae69b2d155a1f67bdb3ce34996796d90
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2023-02-01 15:03:53 +08:00
Jon Lin
b5c957981c dt-bindings: spi: spi-rockchip: Add description for rockchip,poll-only property 
Change-Id: Ie007e5ec889398f662ac32ab36a668cadda23c61
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2023-02-01 15:03:53 +08:00
Jon Lin
a35843d230 spi: rockchip: Support cpu polling to complete transmission 
The default is DMA and IRQ transmission mode. You can change the
transmission mode to only support cpu polling transmission by adding
"rockchip,poll-only" to the device-tree node.

Change-Id: Icee3f4e899533ee51caab68fb85ec45f64b89d91
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
 2023-02-01 15:03:53 +08:00