Commit Graph

839299 Commits

Author SHA1 Message Date
Shawn Lin
de208e40d9 mmc: porting legacy tactices into 4.19
Change-Id: Ieb0e609f5cad4e889be6194f8fd8a54057a1174b
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
2019-02-25 15:19:06 +08:00
Xu Jianqun
03d96331f1 clk: rockchip: add clock ids for vip of RK3368 SoCs
Change-Id: I73ac0fd0010d0dc95c6da0770f85d7b35a11a628
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2019-02-22 18:11:08 +08:00
Xu Jianqun
00c75f4839 clk: rockchip: remove CLK_IGNORE_UNUSED from rk3368 usb otg clocks
Change-Id: Iea6c2e8cd011bcaab30c6f6ce2ed7a9ab7a8711c
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2019-02-22 18:11:08 +08:00
Xu Jianqun
e6e05d2b33 clk: rockchip: add HCLK_USB_PERI for rk3368 usb
Change-Id: Ib1fad4af45ac5ba42ddd97918385aee3bd58e18e
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2019-02-22 18:11:07 +08:00
Xu Jianqun
ba22cd12d4 clk: rockchip: add SCLK_CRYPTO for rk3368 crypto
Change-Id: I5ea4bca3e164df50e720ef748f8ece4511330d70
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2019-02-22 18:11:07 +08:00
Xu Jianqun
3db3717c1e clk: rockchip: rk3368 plls' supports 1188MHz
Since HDMI needs clock rate 74.25MHz, so plls must support
a multiple of it.

For Rockchip rk3368 pll has better jetter with 1188MHz, so
add 1188MHz support.

Change-Id: I68c7333ae076ecabf8637298ee8ca43149cb17d1
Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2019-02-22 18:11:07 +08:00
Jianqun xu
fcdeca01d1 clk: rockchip: add and use clock id for mipi dsi 24M clock
Add dt-binding for mipi dsi 24M clock, and use it.

Change-Id: I1f4dfac958b8b5dacfa6da02151dc3d6a2bd27a7
Signed-off-by: Jianqun xu <jay.xu@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2019-02-22 18:11:07 +08:00
Jianqun xu
23d9961a87 clk: rockchip: rk3368: use the clock IDs for DPHY clocks
The DPHY(DSI PHY) in Rockchip rk3368 supports MIPI/TTL/LVDS
mode. Use the clock IDs (PCLK_DPHYRX and PCLK_DPHYTX0) for
DPHY clocks.

Change-Id: I6a133d6da839d6545e507f38b361b3457e5ff3ee
Signed-off-by: Jianqun xu <jay.xu@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2019-02-22 18:11:07 +08:00
Jianqun xu
d12a79c0ac clk: rockchip: rk3368: add dt bindings for DPHY clocks
Add two clock IDs for DPHY clocks of Rockchip rk3368 SoC.

Change-Id: Iaae4da4a0ea9f4dee2b04fb8eb4f9400bd86511f
Signed-off-by: Jianqun xu <jay.xu@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
2019-02-22 18:11:07 +08:00
Huibin Hong
d15ef7c591 soc: rockchip: grf: unmask uart dma request for RK3308 Soc
Change-Id: I06d955d92d04785bea3248b82fe99c515d471467
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-22 14:38:05 +08:00
Huibin Hong
9219340e40 irqchip/gicv2/3: add gic_retrigger
Change-Id: Ic87d4936317fb598c04e3ccc56a850c0c9e4e6ba
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-22 14:36:13 +08:00
Huibin Hong
e480347688 serial: 8250: enable Programmable THRE Interrupt for tx
Programmable THRE Interrupt mode in order to increase system
performance.

Change-Id: Ic1ef9ecae0c6feb00170ad97ee3c6245ca3bf068
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-22 14:31:44 +08:00
Huibin Hong
68ae37643a serial: 8250: support rx dma mode only
Most SOCS have only 8 or 6 channels, but have more than 16
peripherals. If those peripherals work together, some
fails to request dma channel, because there are no enough
channels. And maybe it's unnecessary to use dma for uart
tx. It is necessary for uart rx when hardware auto flow
control is not used.

&uart0 {
	dma-names = "!tx", "rx";  // disable uart tx with dma
	status = "okay";
};

Change-Id: Ia74477514ba57300a4d19a5c2565ae7b5b8ab521
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-22 14:31:44 +08:00
Huibin Hong
e019b9df43 serial: 8250_dma: support rockchip dma transfer
Change-Id: I0735c41c7d55770eb24c6dede62d623ae8285bdd
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-22 14:31:44 +08:00
Huibin Hong
064129e223 serial: 8250_dw: lost one byte sometime when receive
To avoid "too much work for irq" issue, cherry pick the the patch.
It reads the RBR to clear the time out interrupt, but sometime the
rx fifo may be not empty while cpu reads the RBR. Which would cause
the data lost.

patch for "too much work":06451e93ab59e5b1843c29cbb468a274f4919563

By the way, current patch can't get rid of the risk entirely, so I
try a lot to solve it. Unfortunately, I only got the phenomenon that
lower pclk can reduce the probability. And I check the dw data sheet,
it has pclk and sclk, so there is synchronization problem. But it
only requires (slck < 4*pclk).

Change-Id: I01a36c689b43310294c45294abcf4982f5ddf2af
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-22 14:31:44 +08:00
Huibin Hong
b2aec6e19d serial: 8250_dw: clear time out interrupt when in dma mode
Change-Id: Iebeacce7cea7be8a71ae0dad17db5bcdeb26d52a
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-22 14:31:44 +08:00
Huibin Hong
584044d78b serial: 8250_dw: new baud rate and clk solution
baud rate <=1500000, except 1152000, use 24MHz
baud rate > 1500000, and 1152000 use pll

Change-Id: I9f52fcafdf8cc3d32be78f8408ab75873ffff680
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-22 14:31:44 +08:00
Huibin Hong
f453308641 serial: 8250_dw: set uart clk according to buadrate
Change-Id: I27f92816b202bbe4fa9d97f7656721661afbaa6e
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-22 14:31:44 +08:00
Huibin Hong
f047159701 Bluetooth: hci_ldisc: fix race between open, close and send data
Fix the bug below, it may be reproduced after open and close bt about 7000 times:

<1>[73036.938137] Unable to handle kernel NULL pointer dereference at virtual address 0000001c
<1>[73036.939316] pgd = ffffff800886d000
<1>[73036.939627] [0000001c] *pgd=000000000fffe003, *pud=000000000fffe003, *pmd=0000000000000000
<0>[73036.940396] Internal error: Oops: 96000006 [#1] PREEMPT SMP
<4>[73036.940899] Modules linked in:
<4>[73036.941193] CPU: 2 PID: 2989 Comm: kworker/2:2 Not tainted 4.4.138 #3
<4>[73036.942409] Workqueue: events hci_uart_write_work
<4>[73036.942836] task: ffffffc00d688ac0 task.stack: ffffffc00b184000
<4>[73036.943365] PC is at _raw_spin_lock_irqsave+0x1c/0x50
<4>[73036.943815] LR is at skb_dequeue+0x20/0x74
<4>[73036.944185] pc : [<ffffff8008576398>] lr : [<ffffff800840f9a4>] pstate: 800001c5
<4>[73036.944832] sp : ffffffc00b187d00
<4>[73036.945127] x29: ffffffc00b187d00 x28: 0000000000000000
<4>[73036.945620] x27: 0000000000000000 x26: 0000000000000000
<4>[73036.946114] x25: ffffffc00e1280e0 x24: ffffffc00038d000
<4>[73036.946606] x23: ffffffc00e1271f8 x22: ffffffc00e127f00
<4>[73036.947099] x21: 000000000000001c x20: 0000000000000008
<4>[73036.947592] x19: 0000000000000000 x18: 0000000000000000
<4>[73036.948086] x17: 0000007fade08530 x16: ffffff80080e308c
<4>[73036.948579] x15: 0000000000000000 x14: 65736f6c63207568
<4>[73036.949073] x13: 205d303537373339 x12: 2e36333033375b0a
<4>[73036.949566] x11: 3220746e63666572 x10: 00000000000006f0
<4>[73036.950060] x9 : ffffffc00b187d30 x8 : ffffffc00d689210
<4>[73036.950553] x7 : 0000000000002d31 x6 : 0000000000000400
<4>[73036.951046] x5 : 0000000000113d82 x4 : 0000000000002f32
<4>[73036.951539] x3 : 0000000000000140 x2 : ffffffc00d688ac0
<4>[73036.952032] x1 : 0000000000000001 x0 : 000000000000001c
<4>[73037.068289] [<ffffff8008576398>] _raw_spin_lock_irqsave+0x1c/0x50
<4>[73037.068858] [<ffffff8008377094>] h4_dequeue+0x14/0x1c
<4>[73037.069335] [<ffffff8008376924>] hci_uart_write_work+0x50/0x12c
<4>[73037.069893] [<ffffff80080abbc8>] process_one_work+0x1b0/0x294
<4>[73037.070426] [<ffffff80080ac920>] worker_thread+0x2d8/0x398
<4>[73037.070935] [<ffffff80080b0f28>] kthread+0xc8/0xd8
<4>[73037.071388] [<ffffff8008082e80>] ret_from_fork+0x10/0x50

	thread0               		thread1
	   |				   |
	hci_uart_tty_close		hci_uart_write_work
	   |				   |
	h4_close			h4_dequeue
	   |				   |
	free (h4_struct) h4		   |
	   |             _raw_spin_lock_irqsave access h4 null pointer

Change-Id: I61d8ad5fb4c9349e0a304d2e87332681240f22e2
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-22 14:31:44 +08:00
Huibin Hong
5ea0787207 serial: 8250_dw: uart wake up
Add wakeup-source to uart dts node to enable uart
wake up system when it receives data.

Change-Id: If4e82a4d3dbaca708209553dc3693089864c782f
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-22 14:31:44 +08:00
Huibin Hong
b4541c23c7 serial: 8250: add /dev/ttySx when uart is enable
before the patch:
ls /dev/ttyS
ttyS0 ttyS1 ttyS2 ttyS3 ttyS4 ttyS5  ttyS6 ttyS7

after the patch:
ls /dev/ttyS
ttyS3  ttyS4  ttyS6

Change-Id: I844523408751cb579bbfb50fafb7923d5c2cafdf
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-22 14:31:44 +08:00
Huibin Hong
ad2746d975 serial: 8250: add line error log
Change-Id: I69fe6f0c0857ade25e777be388fcab6261f1a533
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-22 14:31:44 +08:00
Huibin Hong
45de5af8a8 serial: 8250: reset uart when set baud rate
If external device sends data continuously, then uart is
always busy, and baud rate can't be set. It is useful
to reset uart and set loop back mode to make sure it is
idle.

Change-Id: I87286711870ff685ea29e36e61c97d45be5a6d08
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-22 14:31:44 +08:00
Huibin Hong
0f27d1cbb4 serial: 8250: modify warning log about dma request fail
Change-Id: Ib26ef05bb04542ff8d4527a8e7a79cae4dcaa31d
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-22 14:31:44 +08:00
Huibin Hong
2003c94bc0 serial: 8250: set fifo rx trigger 1/2 of fifo
To reduce the uart interrupts, which may cause:

serial8250: too much work for irq xx

Change-Id: I89e0d990677e4cffae431e60521b3e16e8381f05
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-22 14:31:44 +08:00
Huibin Hong
f18548643d serial: 8250_dw: set CPR 0x00023ff2 if it is 0
The UART CPR may be 0 of some rockchip soc,
but it supports fifo and AFC, fifo entry is 32 default.

Change-Id: I44f420c556f703c2848c38dc8449546274ef887d
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-22 14:31:44 +08:00
Frank Wang
243d0b8d2a hid: usbhid: enable hid to wakeup system if it supports remote wakeup
Refer to E.2 (P67) of Device Class Definition for Human Interface
Devices V1.11, the bmAttributes field of the standard configuration
descriptor bit 5 should be set if the HID support Remote Wakeup.

This patch enable the usb HID to wake up the system if the HID
supports remote wakeup.

Change-Id: I169c49ff6187b6400b91633332a72964caca1a94
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit e1653e4dc5)
2019-02-21 09:08:31 +08:00
Tao Huang
6e01437ec4 fiq_debugger: setup_timer() -> timer_setup()
Change-Id: Ia789a1e1d005cf311ab0a7a9e352ec9c9991e30b
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2019-02-19 15:46:04 +08:00
Jeffy Chen
ce9a9e4504 fiq_debugger: Add proc_show like other tty drivers
The userspace might check tty information in proc fs.

Folded following develop-4.4 commit changes into this patch:
77e938e49d ("fiq_debugger: Sanity check state in fiq_tty_proc_show")

Fix for 4.19.

Change-Id: If3e81aacbc7948dd3000606702296bc2b76bec09
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2019-02-19 15:45:11 +08:00
Huibin Hong
6ef6d9e3b6 fiq_debugger: rockchip: deal with this_cpu and current_cpu are different
If this cpu is not the same as current cpu, it means we don't use
current cpu any more, and this cpu handles uart interrupt. So it
is unnecessary to set uart interrupt to this cpu again.

Change-Id: Ia454af96ee766dcbc8b22339652a4aa7eb229568
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-19 15:45:11 +08:00
Huibin Hong
164e4da1f5 fiq_debugger: rockchip: move uart_init to the last
1.When fiq debugger driver probes, and uart rx is pulled low.
The uart interrupt comes so early that uart handler can't be
called. Which makes interrupt come frequently and block the cpu.
2.Remove '<hit enter to activate fiq debugger>'.

Change-Id: I4656d6942bb2cbb0e992852a52bc82f71deadda8
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-19 15:45:11 +08:00
Tao Huang
fce07a27c8 ARM: fiq_glue: fix compilation error for THUMB2_KERNEL
Change-Id: Ia5a7e0c8bcdcc33880f6048d71068a5ccb1c042e
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
(cherry picked from commit ae98ee15abc476711d04b5885848ee6570ee816d)
2019-02-19 15:45:11 +08:00
Tao Huang
5cc432cbd0 fiq_debugger_arm: fix compilation error for THUMB2_KERNEL
Change-Id: Ib1313150393a572b446f9294bc1645ca0d035606
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from commit 70be40088b78d57589c3d999ffd749f41ca31c6e)
2019-02-19 15:45:11 +08:00
Joseph Chen
d8af5c4fa8 fiq debugger: rockchip: fix crash because of invalid sp_el0
(1) use cpu id from bl31 delivers;
(2) sp_el0 should point to kernel address in EL1 mode.

On ARM64, kernel uses sp_el0 to store current_thread_info(),
we see a problem: when fiq occurs, cpu is EL1 mode but sp_el0
point to userspace address. At this moment, if we read
'current_thread_info()->cpu' or other, it leads an error.

We find above situation happens when save/restore cpu context
between system mode and user mode under heavy load.
Like 'ret_fast_syscall()', kernel restore context of user mode,
but fiq occurs before the instruction 'eret', so this causes the
above situation.

Assembly code:

ffffff80080826c8 <ret_fast_syscall>:

...skipping...

ffffff80080826fc:       d503201f        nop
ffffff8008082700:       d5384100        mrs     x0, sp_el0
ffffff8008082704:       f9400c00        ldr     x0, [x0,#24]
ffffff8008082708:       d5182000        msr     ttbr0_el1, x0
ffffff800808270c:       d5033fdf        isb
ffffff8008082710:       f9407ff7        ldr     x23, [sp,#248]
ffffff8008082714:       d5184117        msr     sp_el0, x23
ffffff8008082718:       d503201f        nop
ffffff800808271c:       d503201f        nop
ffffff8008082720:       d5184035        msr     elr_el1, x21
ffffff8008082724:       d5184016        msr     spsr_el1, x22
ffffff8008082728:       a94007e0        ldp     x0, x1, [sp]
ffffff800808272c:       a9410fe2        ldp     x2, x3, [sp,#16]
ffffff8008082730:       a94217e4        ldp     x4, x5, [sp,#32]
ffffff8008082734:       a9431fe6        ldp     x6, x7, [sp,#48]
ffffff8008082738:       a94427e8        ldp     x8, x9, [sp,#64]
ffffff800808273c:       a9452fea        ldp     x10, x11, [sp,#80]
ffffff8008082740:       a94637ec        ldp     x12, x13, [sp,#96]
ffffff8008082744:       a9473fee        ldp     x14, x15, [sp,#112]
ffffff8008082748:       a94847f0        ldp     x16, x17, [sp,#128]
ffffff800808274c:       a9494ff2        ldp     x18, x19, [sp,#144]
ffffff8008082750:       a94a57f4        ldp     x20, x21, [sp,#160]
ffffff8008082754:       a94b5ff6        ldp     x22, x23, [sp,#176]
ffffff8008082758:       a94c67f8        ldp     x24, x25, [sp,#192]
ffffff800808275c:       a94d6ffa        ldp     x26, x27, [sp,#208]
ffffff8008082760:       a94e77fc        ldp     x28, x29, [sp,#224]
ffffff8008082764:       f9407bfe        ldr     x30, [sp,#240]
ffffff8008082768:       9104c3ff        add     sp, sp, #0x130
ffffff800808276c:       d69f03e0        eret

Change-Id: I071e899f8a407764e166ca0403199c9d87d6ce78
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
2019-02-19 15:45:11 +08:00
Huibin Hong
da3351f894 fiq_debugger: use __handle_sysrq instead of handle_sysrq
Because init.rc does the following operation, handle_sysrq
will do nothing. If we want to use sysrq, __handle_sysrq
can work.
write /proc/sys/kernel/sysrq 0

Change-Id: Ia51debd92f393326f183736e405e25dc4d6a2abc
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-19 15:45:11 +08:00
Huibin Hong
e3d8bd2325 fiq_debugger: merge from linux 3.10
update some features:
1. rename sip smc function name;
2. add serial hw irq and phyical base address parse;
3. use FIQ_DEBUGGER_TRUST_ZONE for armv7 and armv8.

Change-Id: I920899f30cadf1ec8380a2e70f5d1e0e801ec5c2
Signed-off-by: chenjh <chenjh@rock-chips.com>
2019-02-19 15:45:11 +08:00
Huibin Hong
a8ac8469aa fiq_debugger: Switch current cpu when the former cpu is offline
Change-Id: Ie1a5fe5c3496e5182f0f9aaab336a4d0ff683dfa
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-19 15:45:11 +08:00
Huibin Hong
aa9c50133f fiq_debugger: do reboot_notifier for reset command
Change-Id: I31e0789e7a7ed8cd645d103abc20a21fc3140f36
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-19 15:45:11 +08:00
Huibin Hong
44f5b21367 fiq_debugger: print log by console thread
Change-Id: Id664cdfe02f87b1f8bb37b9a4e3985c1eafef226
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-19 15:45:11 +08:00
Huibin Hong
418432c868 soc: rockchip: add rk fiq debugger platform driver
Change-Id: Ibb32efc190ce49d657973133a30632c71f0d806c
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
2019-02-19 15:45:11 +08:00
Tao Huang
8396e1599d soc: rockchip: rk_fiq_debugger: support 4.19
cpu hotplug register to hotplug state machine.
use subsys_initcall.

Change-Id: I65431a7b22bf8dcd9b5d4c4a6c4967251038486e
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
2019-02-19 15:45:11 +08:00
Dmitry Shmidt
cf896fb66f UPSTREAM: ANDROID: fiq_debugger: Remove wakelock.h dependencies
Change-Id: I16a0dd4c4c6ee6440ce8a921bc0834d904b81f37
Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from https://android.googlesource.com/kernel/common:android-4.14
 commit f9cbd12ed7051fb82e0e584947a6eb8f3dcbf7cf)
2019-02-18 16:14:36 +08:00
Dmitry Shmidt
6b0395671e UPSTREAM: ANDROID: fiq_debugger: Add fiq_debugger.disable option
This change allows to use same kernel image with
different console options for uart and fiq_debugger.
If fiq_debugger.disable will be set to 1/y/Y,
fiq_debugger will not be initialized.

Change-Id: I71fda54f5f863d13b1437b1f909e52dd375d002d
Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from https://android.googlesource.com/kernel/common:android-4.14
 commit 76d292f95a217b4ba236fd2db858ac99295fd832)
2019-02-18 16:14:35 +08:00
Dmitry Shmidt
a5e1fd5c5a UPSTREAM: ANDROID: fiq_debugger: Add option to apply uart overlay by FIQ_DEBUGGER_UART_OVERLAY
fiq_debugger is taking over uart, so it is necessary to disable
original uart in DT file. It can be done manually or by overlay.

Change-Id: I9f50ec15b0e22e602d73b9f745fc8666f8925d09
Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from https://android.googlesource.com/kernel/common:android-4.14
 commit 0ff9e291c1181f124a4ea58ce95f09b7acb735cc)
2019-02-18 16:14:34 +08:00
Arve Hjønnevåg
a8f5f5eb1a UPSTREAM: ANDROID: fiq_debugger: Add fiq_watchdog_triggered api
Dumps registers and stacktrace into console-ramoops when called
from a watchdog fiq.

Change-Id: Ib6fab5a52f670db18e64214d5e4890e8292a749c
Signed-off-by: Arve Hjønnevåg <arve@android.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from https://android.googlesource.com/kernel/common:android-4.14
 commit 9c027e6c233a5d2eace40b6394dd7641afff33bb)
2019-02-18 16:14:33 +08:00
Arve Hjønnevåg
e4df234d50 UPSTREAM: ANDROID: fiq_debugger: Call fiq_debugger_printf through a function pointer from cpu specific code
This allows the output from the register and stack trace code to be
sent elsewhere.

Change-Id: I41bb0d5a25e1b9ca55feef5dbd675818b2f832d5
Signed-off-by: Arve Hjønnevåg <arve@android.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from https://android.googlesource.com/kernel/common:android-4.14
 commit 9200a45dc9e0007ec7192db0e78817850876ed68)
2019-02-18 16:14:32 +08:00
Colin Cross
f7b6cc8cb6 UPSTREAM: ANDROID: fiq_debugger: add ARM64 support
Add fiq_debugger_arm64.c that implements the platform-specific
functions.

Change-Id: I4d8b96777bb8503a93d4eb47bbde8e018740a5bf
Signed-off-by: Colin Cross <ccross@android.com>
[AmitP: Remove unused stackframe -> sp to align with upstream commit
        31e43ad3b7 ("arm64: unwind: remove sp from struct stackframe")
        Also folded following android-4.9 commit changes into this patch
        a33d9f9fa3 ("ANDROID: fiq_debugger: Pass task parameter to unwind_frame()")]
Signed-off-by: Amit Pundir <amit.pundir@linaro.org>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from https://android.googlesource.com/kernel/common:android-4.14
 commit c9d6bc7ab0a4360f79418aa16f3cd68ac2f57a40)
2019-02-18 16:14:31 +08:00
Colin Cross
d59dab4503 UPSTREAM: ANDROID: fiq_debugger: split arm support into fiq_debugger_arm.c
Split arm support into a separate .c file that is only built for
CONFIG_ARM.

Change-Id: Iba16f4d51608bf9c3e5c8acefefcd38fead9797c
Signed-off-by: Colin Cross <ccross@android.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from https://android.googlesource.com/kernel/common:android-4.14
 commit efffceb1e926e6210d51eaaa62ce3f3be8a5fab7)
2019-02-18 16:14:30 +08:00
Colin Cross
e092157257 UPSTREAM: ANDROID: fiq_debugger: use pt_regs for registers
IRQ mode already passes in a struct pt_regs from get_irq_regs().
FIQ mode passes in something similar but not identical to a
struct pt_regs - FIQ mode stores the spsr of the interrupted mode
in slot 17, while pt_regs expects orig_r0.

Replace the existing mixture of void *regs, unsigned *regs, and
struct pt_regs * const with const struct pt_regs *.  Modify
dump_regs not to print the spsr since it won't be there in a
struct pt_regs anyways.  Modify dump_allregs to highlight the
mode that was interrupted, making spsr easy to find there.

Change-Id: Ibfe1723d702306c7605fd071737d7be9ee9d8c12
Signed-off-by: Colin Cross <ccross@android.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from https://android.googlesource.com/kernel/common:android-4.14
 commit bf32f8accce8701e896879fee463e5b07cbeb8b9)
2019-02-18 16:14:29 +08:00
Colin Cross
c8e4b7bace UPSTREAM: ANDROID: fiq_debugger: allow compiling without CONFIG_FIQ_GLUE
Allow compiling fiq_debugger.c without CONFIG_FIQ_GLUE for
platforms that don't support FIQs.

Change-Id: Iabdfd790d24fa9d47b29d2f850c567af2dcad78f
Signed-off-by: Colin Cross <ccross@android.com>
Signed-off-by: Tao Huang <huangtao@rock-chips.com>
(cherry picked from https://android.googlesource.com/kernel/common:android-4.14
 commit 16c3248941c0f6ee3766fc0d36e0248c6f0cdfb5)
2019-02-18 16:14:27 +08:00