PD#SWPL-8467
Problem:
1.no index parse for edid data block
2.no earc capabilities data structure parse
3.no earc cap data structure splice function
4.no cta data block splice/remove function
Solution:
1.add edid data block index parse
2.add earc capabilities data structure parse
3.add splice function of earc cap data structure
4.add splice/remove function of data block to edid
Verify:
TL1
Change-Id: I47b9f2176c31c65a08cdc657c00398f88cbdd7d3
Signed-off-by: Hang Cheng <hang.cheng@amlogic.com>
PD#SWPL-7952
Problem:
vdin0 cma_size is not enough for some board
Solution:
1.change hdmirx skip_vf_num to 1.
2.increase vdin0 cma_size to 200M for 4k YUV444 10bit support,
other resolution usage will be lower,
such as 4k YUV422 10bit 160M.
Verify:
ab301
Change-Id: I353e2f9e5e6a25c8c3a34e10813039e9bba7e4a6
Signed-off-by: Evoke Zhang <evoke.zhang@amlogic.com>
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
Conflicts:
arch/arm64/boot/dts/amlogic/tm2_t962x3_ab301.dts
PD#SWPL-6792
Problem:
EDID buff change to independent mode for each port
Solution:
1. add new edid update method
2. fix dv status issue for dv10
Verify:
Verfied on TM2 skt board
Change-Id: I274e5c08168b79fcfab0d2575a6531ab9802af3f
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
PD#SWPL-7084
Problem:
hdmirx signal detection time is long
Solution:
Optimize the phy pll init logic
Verify:
TL1
Change-Id: Ibdfdb3a54d2a5cbdf4f6292b85616fdba36c37a9
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
PD#SWPL-8032
Problem:
Switching to HDMI source is slower than T962
Solution:
ensure pll lock is table before do DWC reset
Verify:
T962X2
Change-Id: I1133d6b1fb532ab8460c1906a021fe133ea9fb83
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
PD#SWPL-6400
Problem:
need sync code with mainline
Solution:
sync mainline's print and coding style
Verify:
verify by marconi
Change-Id: I1934cf01f8e1ff87a0c9ab59a7288d2b6edaff84
Signed-off-by: Lei Qian <lei.qian@amlogic.com>
PD#SWPL-7452
Problem:
TV is no signal when turn off and turn on dishNXT box
Solution:
clear hdcp avmute status if hdcp is not start
Verify:
962X
Change-Id: I0448e46baea4f8666b2b665f6c867fecb41fb7d0
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
PD#SWPL-6400
Problem:
hdmirx phy clk_out is not stable,and causes long detection time
Solution:
VLSI provide a new PLL init sequence
Verify:
TL1
Change-Id: I42b98572226aafc8e61e36b6a2e5dfad078fd8fe
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
PD#SWPL-7570
Problem:
there's frequent interrupt when suspend, and can't
enter suspend successfully
Solution:
disable interrupt when suspend/shutdown
Verify:
x301
Change-Id: Iad13159da8cf0d48c6374c17df957c26aa177024
Signed-off-by: Hang Cheng <hang.cheng@amlogic.com>
PD#SWPL-6785
Problem:
there's garbage frame show when signal change
Solution:
enable forward video frame skip interface, and set vdin
to skip one more frame to prevent garbage been shown
Verify:
X301
Change-Id: Id099558c733843f330b99246ea31fbbd0c18ed84
Signed-off-by: Hang Cheng <hang.cheng@amlogic.com>
Conflicts:
drivers/amlogic/media/vin/tvin/hdmirx/hdmi_rx_wrapper.c
PD#SWPL-6360
Problem:
Connect PS4PRO,plug out than in,the audio will show faster than video.
Solution:
1.update CDR lock logic;
2.add sw_reset_align and sw_reset_chan;
3.update phy init sequence;
Verify:
TL1
Change-Id: I0ef259502579a7edd2c61708c81983ce07124c9f
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
PD#SWPL-6234
Problem:
flash line in the screen when HDMI connect iTV IV3010 box.
Solution:
1.update phy low frequency setting;
2.optimzie pll init sequence to save some detection time;
3.update verB pll setting(0323);
Verify:
TL1
Change-Id: I71225b06f02e4888ce093780a2beb0a381986293
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
PD#SWPL-4308
Problem:
gpu limit cause cts performance test fail
Solution:
limit gpu only when video playing or hdmiin
Verify:
P321
Change-Id: I682a908957491c8445fdb384dedd404169757e2b
Signed-off-by: wenbiao zhang <wenbiao.zhang@amlogic.com>
PD#SWPL-5668
Problem:
recognized as dvi after suspend/resume
when connect xiaomi mtk box
Solution:
when resume, add rxsense pulse to avoid
sda pulled low by xiaomi mtk box
Verify:
TL1-T962X2_X301
Change-Id: I480cbb4376bbb0c3b38318df2e26f5cc85db3d59
Signed-off-by: Hang Cheng <hang.cheng@amlogic.com>
PD#SWPL-5813
Problem:
HBR audio cannot work on TL1
Solution:
add a debug interface force hdmi afifo in 8ch mode
Verify:
t962x2
Change-Id: Ied02f772634e2c326e18f6d6463c0ae000430e29
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
PD#SWPL-5579
Problem:
audio fifo underflow after switch audio pattern
on chroma 2233: only 2ch audio in, but audio fifo
is configed to read out 8ch afifo. chroma 2233
may change from multi-channel(witch audio overflows
and workaround to config read out all subpackets)
to 2-channel audio pattern, then issue happens.
so need to reset audio fifo config.
Solution:
except for workaround case, always config audio
fifo to only store valid subpackets.
Verify:
tl1
Change-Id: If32a55330fa7ebd9f6359a460eea4ad62872207b
Signed-off-by: Hang Cheng <hang.cheng@amlogic.com>
PD#SWPL-4981
Problem:
it_content info is not correct
Solution:
optimize the method for getting it content
Verify:
TL1
Change-Id: Ie9202b6496742af6d880ae22f3f8f6154db8629a
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
PD#SWPL-4325
Problem:
it took long time to show image when connect with Google Chromecast box
Solution:
1. add specific dev detection by cec osd name & vendor ID
2. chromecast box force OESS
Verify:
verify by marconi
Change-Id: I56d247da1d1b1e28b60bb439f5173cb6fbecfdf9
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
hdmirx: Chromecast box force to OESS mode [1/1] (Partial)
PD#SWPL-4325
Problem:
it took long time to show image when connect with Google Chromecast box
Solution:
1. add specific dev detection by cec osd name & vendor ID
2. chromecast box force OESS
Verify:
verify by marconi
Change-Id: I56d247da1d1b1e28b60bb439f5173cb6fbecfdf9
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
PD#SWPL-4261
Problem:
some devices have compatibility issues.
Solution:
1.update phy setting;
2.optimize some SW logic;
3.set eess_oess to auto mode;
4.fix black screen(DE fixed error,related with rx phy) issue.
Verify:
TL1 TXLX android P
Change-Id: I842a4782b3e513fa1e483feca98ce05b128d79fc
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
PD#SWPL-4088
Problem:
There will be kernel panic when read edid via hdmirx
driver interface
Solution:
modify the rd_top interface
Verify:
TL1 android P
Change-Id: Ifb595cc66a2e792bc5153d726258deb7ba4e741c
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
PD#SWPL-4073
Problem:
warning of CPU Tainted
Solution:
add spin lock when R/D reg
Verify:
verify by marconi
Change-Id: I8f47666f41c0ba3a010631f5d71416aad0e43beb
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
PD#SWPL-3828
Problem:
hdcp22 access ddr when power shutdown
Solution:
need notify hdcp22 close when power shutdown
Verify:
Local
Change-Id: Iffead6b2dfdd97e6e7ad16e856cb09b42e3783d1
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
PD#SWPL-3360
Problem:
hdcp_rx22 ocupy much of CPU resources.
Solution:
Optimize the method of hdcp_rx22 polling-rx-status function.
Verify:
Local
Change-Id: If1c54b9cc219e32f349b4f4c555fb3fbd3539491
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
PD#SWPL-3540
Problem:
rxsense is high ahead off hpd high, some device
may start hdcp, but hdcp auth always fail
Solution:
set rxsense sync with hpd
Verify:
TL1
Change-Id: I94b4c4f188587e15bac6aceb70803a3aa9082d3b
Signed-off-by: Hang Cheng <hang.cheng@amlogic.com>
PD#SWPL-3117
Problem:
Cannot get the HDR packets/
Solution:
add HDR RCV detection, Low priority than EMP.
Verify:
txlx tl1
Change-Id: I364fc942840b6eef465df16b89fd0a9fd0ccb3ff
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
PD#TV-1212
Problem:
the power comsuption is too high for hdmirx
Solution:
1.power down the phy at suspend
2.power on the phy at resume
Verify:
x301
Change-Id: I8920a6b38197109d424d225c4b31f5170b56ca08
Signed-off-by: hongmin hua <hongmin.hua@amlogic.com>
PD#172587
Problem:
1.clean phy setting
Solution:
1.put the phy data into a table
2.modify phy setting for low voltage tmds clk
Verify:
tl1
Change-Id: I8cad5d0639f72b17b90196f6143784f7b91dcdbc
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
PD#172587
Problem:
1.eq performacec is not good (v1)
2.capture tmds raw data to ddr
3.skip unstable cable clock report
Solution:
1.dump tmds date and save as a file
2.1s check err counter
3.modify clock monitor function
4.modify fsm for tl1
Verify:
tl1
Change-Id: Iae51ea0cc8528e9c5fd0bc5c58b5dd7246ee68b1
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
PD#172587
Problem:
1.cable clk is not match from clk measure
2.add some debug interface for tl1
Solution:
1.add audio clock source from tmds
2.add audio clock source from mpll
3.low FRQ phy audio clock out is 4xtmds clk
4.add 6G phy setting
5.match clock measure return value hz
6.phy initial enable terminal by input source
7.add channel switch control 0/1
8.last line,mode:4k2k 420 deep color problem
9.dump register, add error cnt for tl1
10.capture emp data into a file
11.modify tmds data align, snps phy disable
Verify:
1.run ptm
2.verify on chip
Change-Id: I9d003748c0df3dfbd25f7ab987449e2097251c58
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
PD#SWPL-2114
Problem:
When change audio channel count on VG-877, the subpkts of skipped
middle channels are still carried, thus causing afifo overflow
Solution:
When afifo overflow, then store all audio subpkts(8ch)
into afifo, and output 8ch audio from afifo
Verify:
R321
Change-Id: I4b0933935d3a1aed20be10a7a8d3fe23c3a39323
Signed-off-by: Hang Cheng <hang.cheng@amlogic.com>
