PD#SWPL-6360
Problem:
Connect PS4PRO,plug out than in,the audio will show faster than video.
Solution:
1.update CDR lock logic;
2.add sw_reset_align and sw_reset_chan;
3.update phy init sequence;
Verify:
TL1
Change-Id: I0ef259502579a7edd2c61708c81983ce07124c9f
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
PD#SWPL-6234
Problem:
flash line in the screen when HDMI connect iTV IV3010 box.
Solution:
1.update phy low frequency setting;
2.optimzie pll init sequence to save some detection time;
3.update verB pll setting(0323);
Verify:
TL1
Change-Id: I71225b06f02e4888ce093780a2beb0a381986293
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
PD#SWPL-4308
Problem:
gpu limit cause cts performance test fail
Solution:
limit gpu only when video playing or hdmiin
Verify:
P321
Change-Id: I682a908957491c8445fdb384dedd404169757e2b
Signed-off-by: wenbiao zhang <wenbiao.zhang@amlogic.com>
PD#SWPL-5668
Problem:
recognized as dvi after suspend/resume
when connect xiaomi mtk box
Solution:
when resume, add rxsense pulse to avoid
sda pulled low by xiaomi mtk box
Verify:
TL1-T962X2_X301
Change-Id: I480cbb4376bbb0c3b38318df2e26f5cc85db3d59
Signed-off-by: Hang Cheng <hang.cheng@amlogic.com>
PD#SWPL-5813
Problem:
HBR audio cannot work on TL1
Solution:
add a debug interface force hdmi afifo in 8ch mode
Verify:
t962x2
Change-Id: Ied02f772634e2c326e18f6d6463c0ae000430e29
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
PD#SWPL-5579
Problem:
audio fifo underflow after switch audio pattern
on chroma 2233: only 2ch audio in, but audio fifo
is configed to read out 8ch afifo. chroma 2233
may change from multi-channel(witch audio overflows
and workaround to config read out all subpackets)
to 2-channel audio pattern, then issue happens.
so need to reset audio fifo config.
Solution:
except for workaround case, always config audio
fifo to only store valid subpackets.
Verify:
tl1
Change-Id: If32a55330fa7ebd9f6359a460eea4ad62872207b
Signed-off-by: Hang Cheng <hang.cheng@amlogic.com>
PD#SWPL-4981
Problem:
it_content info is not correct
Solution:
optimize the method for getting it content
Verify:
TL1
Change-Id: Ie9202b6496742af6d880ae22f3f8f6154db8629a
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
PD#SWPL-4325
Problem:
it took long time to show image when connect with Google Chromecast box
Solution:
1. add specific dev detection by cec osd name & vendor ID
2. chromecast box force OESS
Verify:
verify by marconi
Change-Id: I56d247da1d1b1e28b60bb439f5173cb6fbecfdf9
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
hdmirx: Chromecast box force to OESS mode [1/1] (Partial)
PD#SWPL-4325
Problem:
it took long time to show image when connect with Google Chromecast box
Solution:
1. add specific dev detection by cec osd name & vendor ID
2. chromecast box force OESS
Verify:
verify by marconi
Change-Id: I56d247da1d1b1e28b60bb439f5173cb6fbecfdf9
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
PD#SWPL-4261
Problem:
some devices have compatibility issues.
Solution:
1.update phy setting;
2.optimize some SW logic;
3.set eess_oess to auto mode;
4.fix black screen(DE fixed error,related with rx phy) issue.
Verify:
TL1 TXLX android P
Change-Id: I842a4782b3e513fa1e483feca98ce05b128d79fc
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
PD#SWPL-4088
Problem:
There will be kernel panic when read edid via hdmirx
driver interface
Solution:
modify the rd_top interface
Verify:
TL1 android P
Change-Id: Ifb595cc66a2e792bc5153d726258deb7ba4e741c
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
PD#SWPL-4073
Problem:
warning of CPU Tainted
Solution:
add spin lock when R/D reg
Verify:
verify by marconi
Change-Id: I8f47666f41c0ba3a010631f5d71416aad0e43beb
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
PD#SWPL-3828
Problem:
hdcp22 access ddr when power shutdown
Solution:
need notify hdcp22 close when power shutdown
Verify:
Local
Change-Id: Iffead6b2dfdd97e6e7ad16e856cb09b42e3783d1
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
PD#SWPL-3360
Problem:
hdcp_rx22 ocupy much of CPU resources.
Solution:
Optimize the method of hdcp_rx22 polling-rx-status function.
Verify:
Local
Change-Id: If1c54b9cc219e32f349b4f4c555fb3fbd3539491
Signed-off-by: yicheng shen <yicheng.shen@amlogic.com>
PD#SWPL-3540
Problem:
rxsense is high ahead off hpd high, some device
may start hdcp, but hdcp auth always fail
Solution:
set rxsense sync with hpd
Verify:
TL1
Change-Id: I94b4c4f188587e15bac6aceb70803a3aa9082d3b
Signed-off-by: Hang Cheng <hang.cheng@amlogic.com>
PD#SWPL-3117
Problem:
Cannot get the HDR packets/
Solution:
add HDR RCV detection, Low priority than EMP.
Verify:
txlx tl1
Change-Id: I364fc942840b6eef465df16b89fd0a9fd0ccb3ff
Signed-off-by: Lei Yang <lei.yang@amlogic.com>
PD#TV-1212
Problem:
the power comsuption is too high for hdmirx
Solution:
1.power down the phy at suspend
2.power on the phy at resume
Verify:
x301
Change-Id: I8920a6b38197109d424d225c4b31f5170b56ca08
Signed-off-by: hongmin hua <hongmin.hua@amlogic.com>
PD#172587
Problem:
1.clean phy setting
Solution:
1.put the phy data into a table
2.modify phy setting for low voltage tmds clk
Verify:
tl1
Change-Id: I8cad5d0639f72b17b90196f6143784f7b91dcdbc
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
PD#172587
Problem:
1.eq performacec is not good (v1)
2.capture tmds raw data to ddr
3.skip unstable cable clock report
Solution:
1.dump tmds date and save as a file
2.1s check err counter
3.modify clock monitor function
4.modify fsm for tl1
Verify:
tl1
Change-Id: Iae51ea0cc8528e9c5fd0bc5c58b5dd7246ee68b1
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
PD#172587
Problem:
1.cable clk is not match from clk measure
2.add some debug interface for tl1
Solution:
1.add audio clock source from tmds
2.add audio clock source from mpll
3.low FRQ phy audio clock out is 4xtmds clk
4.add 6G phy setting
5.match clock measure return value hz
6.phy initial enable terminal by input source
7.add channel switch control 0/1
8.last line,mode:4k2k 420 deep color problem
9.dump register, add error cnt for tl1
10.capture emp data into a file
11.modify tmds data align, snps phy disable
Verify:
1.run ptm
2.verify on chip
Change-Id: I9d003748c0df3dfbd25f7ab987449e2097251c58
Signed-off-by: Yong Qin <yong.qin@amlogic.com>
PD#SWPL-2114
Problem:
When change audio channel count on VG-877, the subpkts of skipped
middle channels are still carried, thus causing afifo overflow
Solution:
When afifo overflow, then store all audio subpkts(8ch)
into afifo, and output 8ch audio from afifo
Verify:
R321
Change-Id: I4b0933935d3a1aed20be10a7a8d3fe23c3a39323
Signed-off-by: Hang Cheng <hang.cheng@amlogic.com>
PD#SWPL-8231
Problem:
When HDMI cable plugin, the SDA may hold low forever or for short time.
Solution:
Add sw_reset_flt reset to resolve hold low forever issue
Verify:
G12/Dongle
Change-Id: I53bbf704bb48a2cd3cc2ebef1444c69ad1623e87
Signed-off-by: Zongdong Jiao <zongdong.jiao@amlogic.com>
PD#SWPL-13664
Problem:
when open some special UI app, DI will have a lot of timeout,
this cause display abnormal.
Solution:
add retry after timeout;
Verify:
tl1
Change-Id: I3316252577bad218256651ebbc6d4fd8b25acb12
Signed-off-by: Jihong Sui <jihong.sui@amlogic.com>
PD#SWPL-12002
Problem:
pause and plug out/in hdmi tx, display abnormal
Solution:
add condition for switch to EI in de_post_process
ref to IPTV's project
Verify:
G12A
Change-Id: I6230464c308660c62199aa24ad5843e7c7bd070d
Signed-off-by: Jihong Sui <jihong.sui@amlogic.com>
PD#SWPL-13223
Problem:
there is a white line on left when crop left is odd
Solution:
set post mif phase to 8;
Verify:
TL1
Change-Id: Ic39e15f5c1d07e756ecc4909366af35d1472dc29
Signed-off-by: Jihong Sui <jihong.sui@amlogic.com>
PD#SWPL-11555
Problem:
there is jaggy in the seek process
Solution:
add condition for recycle mirror buf
Verify:
TL1
Change-Id: I13c17fd78386ef2cb5f44b4e8c33be3fa92e31e2
Signed-off-by: Jihong Sui <jihong.sui@amlogic.com>
PD#SWPL-12404
Problem:
red and green stripes dividing line flash black line
Solution:
close cue(422/444) except local play(420)
VLSI-yanling suggest
Verify:
TL1
Change-Id: Ied1554d6a0e64e00aea1e692ab6b405f87387095
Signed-off-by: Jihong Sui <jihong.sui@amlogic.com>
PD#SWPL-10064
Problem:
Prepare for adding multi-di
Solution:
1. add di_local for reserved mem alloc;
2. add dil_attach_ext_api for di_api;
3. move some setting to prob;
4. add interface for di pq;
Verify:
U212
Change-Id: I023694dffabed47fd62ec3fa90b8de9302ac341e
Signed-off-by: Jihong Sui <jihong.sui@amlogic.com>
Conflicts:
MAINTAINERS
PD#TV-8024
Problem:
abnormal display in small window.
Solution:
turn off afbc temporary.
Verify:
tl1
Change-Id: I6f863330ed9261ef00b0d1c7bdeaa341a9aaa2ca
Signed-off-by: Jihong Sui <jihong.sui@amlogic.com>
PD#SWPL-11389
Problem:
PQ need work around for 1080i(based on VLSI's suggestions)
co-work with yanling/mingliang
Solution:
add pulldown information to vframe;
u32 di_pulldown:
-bit 3: interlace
-bit 2: flmxx
-bit 1: flm22
-bit 0: flm32
Verify:
TL1
Change-Id: I9ff06ffa7aaa9516a3e64cec9768272499678fd5
Signed-off-by: Jihong Sui <jihong.sui@amlogic.com>
PD#SWPL-15631
Problem:
There is an error in
c62207ef53
Solution:
correct the err
Verify:
SM1
Change-Id: If645ee88533dab7e28ff95d578be019a2cb894a6
Signed-off-by: yao liu <yao.liu@amlogic.com>
PD#SWPL-14902
Problem:
Play HDR video locally, after exiting, the screen flashes 1, 2 seconds
Solution:
set rdma_hdr_delay default value to 0
Verify:
Verified by T962-P321
Change-Id: I9c0a56332e38d1238129e682535f588104faf8be
Signed-off-by: Pengcheng Chen <pengcheng.chen@amlogic.com>
PD#SWPL-14256
Problem:
When ATV Mode has no signal
the bright line interference at the bottom
if freescale height is set to vinfo height
Solution:
modify VPP_OSD_SC_DUMMY_DATA alpha value
Verify:
verified on txlx-r311
Change-Id: I48bbb1be533a88e8b3c622550a0a2e8c07f2a863
Signed-off-by: Cao Jian <jian.cao@amlogic.com>
PD#TV-6994
Problem:
When ATV Mode has no signal
the bright line interference at the bottom
Solution:
modify VPP_OSD_SC_DUMMY_DATA alpha value
Verify:
verified on txlx-r311
Change-Id: Icc5039f80bd794ed5adb98e22fbf41f52758ef83
Signed-off-by: Jian Cao <jian.cao@amlogic.com>
PD#SWPL-11936
Problem:
set screen position frequently
frame flashes white stripes
Solution:
modify threshold for updating all registers
on vsync coming
Verify:
Verfied on u212
Change-Id: Iac1ec8b5ec36809d5f5ffe2fe8e79c182e9c126b
Signed-off-by: Cao Jian <jian.cao@amlogic.com>
