Extend the existing color management properties to support provision
of a 3D cubic look up table, allowing for color specific adjustments.
Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Co-developed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Change-Id: I0bda1203a10f0df978b767d29baf06b390c0867e
Link:
https: //lore.kernel.org/dri-devel/20201221015730.28333-4-laurent.pinchart+renesas@ideasonboard.com/
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Before vop 2.0, the display sub system only
support one RGB/LVDS/eDP/HDMI/MIPI connector
for one vop, so we can find which output interface
should be enabled by output_type(DPI/LVDS/HDMI).
But for the VOP 2.0 display subsystem, we may
have two connector (LVDS/eDP/HDMI/MIPI) of the
same output_type(HDMI0,HDMI1) enabled at same time,
so the output_type is not enough to give the interface
information, we need to know HDMI0 or HDMI1, eDP0 or eDP1
should be enabled.
So we add output interface id here, every connector
driver should set it correctlly to tell vop driver
to enable the corresponding output interface.
Change-Id: Ic22863f0f18f160b0df7d8f4c3b71b17ef987ea9
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Add the clock tree definition for the new rk1808 SoC.
Change-Id: I86e502b27e0695c77e9937dfd7cffa14b5711954
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
remove the buf[0] & HYM8563_SEC_VL, it's unsuitable for some hym8563.
set rtc init time for first power on.
Change-Id: Iaa207d554d9df9ad8f138fc2f196c8a7a991b141
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add /proc/clk/
summary: dump clk tree
rate: set clk rate by clk name
enable: enable/disable clk by clk name
parent: set clk parent
Change-Id: Iea0570e74a410a05b3bd29dcd2816dd1320d4ff5
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The RK3568 SoCs have two Temperature Sensors, channel 0 is for CPU,
channel 1 is for GPU.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I0dde1dabfbc1bf44ca203cfdea896ca0c05dfadf
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Get the calibration parameters for each chip by reading the OTP,
Calculate temperature using calibration parameters.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I05cfb65ae95dcefc7fc52ed91326c7da9d27de55
RV1126 tsadc bandgap chopper function should be configured,
add a new initialize function to handle this for RV1126 SoCs.
RV1126 tshut mode also need select the tshut type in GRF regs,
add a new set mode function to handle this for RV1126 SoCs.
Change-Id: I81106539362bc32e0d8aaeeb0398d1bcb33b6b60
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
RV1126 SOC has two independent Temperature Sensors for CPU and NPU.
RV1126 TSADC clock design has been updated, added the PHY clock,
using the group managed clocks.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I395daa3b591390980a11ea7eed827c0e297f6ebe
Fixed the panic reloads when there are multiple thermal devices.
Change-Id: Ia08b0bfec940be089440b9246cc1abf9626c19a7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add a new compatible for thermal founding on RV1126 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I84e7ca521f4edce9516575bd54709326e62fc85c
Based on the TSADC Tshut mode to select pinctrl,
instead of setting pinctrl based on architecture
(Not depends on pinctrl setting by "init" or "default").
And it requires setting the tshut polarity before select pinctrl.
Change-Id: Iac9ca05073b0181ee13b0048d0c2a54204f82bca
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The cpll clk gate bits had an ordering issue. This led to the loss of
the boot sdmmc controller when the gmac was shut down with:
`ip link set eth0 down`
as the cpll_100m was shut off instead of the cpll_62p5.
cpll_62p5, cpll_50m, cpll_25m were all off by one with cpll_100m
misplaced.
Fixes: e9ac850b88 ("clk: rockchip: add clock controller for rk3568")
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://patchwork.kernel.org/project/linux-clk/patch/20210519174149.3691335-1-pgwipeout@gmail.com/
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I012bdbdc44c4e8de1b42a00c2a9bffb7bd66faef
This patch set attempts to new compatible for thermal founding
on RK1808 SoCs.
Change-Id: I133218cd958e0aabf711a5d22fe5e5da2fbd59ce
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Based on the TSADC Tshut mode to select pinctrl,
instead of setting pinctrl based on architecture
(Not depends on pinctrl setting by "init" or "default").
And it requires setting the tshut polarity before select pinctrl.
Change-Id: Ieb181ec19dedbbfb7aef474b3558aac867e668eb
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Tsadc has a tshut pin which is designed to reset the pmic or soc,
when the temperature inside soc is too high. we should switch off
the tshut function and change the pin to gpio function in reboot
process, eg, software reset. If not, the tsadc module will WRONGLY
pull high the tshut pin during its reset process and then WRONGLY
reset the pmic or soc, which incurred a hardware reset. The hardware
reset will reset everything inside soc, even includes the power on
reason flag, which is set by software before reboot process.
we also change over-temperature protection mode to cru mode,
since the tshut pin have be changed to gpio function.
Change-Id: Iac3dacf55a4b5536fccd2eb05a6a9e6923a082c0
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Switch is just a function of switching. There is no voltage setting
function. Voltage getting is the supply voltage.
Fixes: aea6cb9970 ("regulator: resolve supply after creating
regulator")
Change-Id: I22ff04b59b9b051052348420f25999dae424d4ac
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Document the regulator and add a rockchip vendor-prefix.
Change-Id: I3084f2083644e30145ccda2e13e2e81c6470797a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add cru regs dump when system panic.
It's just for debug.
Change-Id: Ic60f491d549e030490c14ea78f4857a8cead596d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add cru regs dump when system panic.
It's just for debug.
Change-Id: I7f9bc78deef60b1fa48bada5b1a6203185ddce48
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add cru regs dump when system panic.
It's just for debug.
Change-Id: Ic4efc985892cbcc5e561203fe8e00dba116439e7
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add cru regs dump when system panic.
It's just for debug.
Change-Id: Ide2c3e8add083934672f6d22d8182bcfde046783
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add cru regs dump when system panic.
It's just for debug.
Change-Id: I86ff4f12ed932431d131d22a307360418e2e9f40
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The pwm clk parent is GPLL,PWM clk not allowed to change freq,
so the GPLL not allowed change mode and freq when pwm is used.
If have trust is need't rk3288_clk_suspend and rk3288_clk_resume.
Change-Id: I4845fda89d7ae7713e8c0e94747c3f4dfd140c6a
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Avoid disable the parent clock after the child clock has disabled.
Change-Id: I1ea91afe0b6bbefd3a5d8e88641e4a3af5a368a4
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
crypto and dmac share the same noc clk,
so mark the aclk_dmac1 as critical clk.
Change-Id: I34a4a7cc532a385086679fafb961a47b0a6abc3b
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
crypto and dmac share the same noc clk,
so mark the aclk_dmac_bus as critical clk.
Change-Id: Ib0b70bbed3fdefeab7b6f2b5f88350a416e66787
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
npll is just for dclk_vop, others clk not allowed to set npll as parent.
Change-Id: I11e1770acab5486acaebafd56a0c57847f7f533c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
with the NB parameter,can adjust the jitter of the output PLL.
make the npll jitter is better,make it more suitable for DCLK display.
Change-Id: I9d819bdc2b520205a7d63ee8ed83643601ccc821
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
