after this commit, axi id is used as the following rules:
AXI0
Cluster0:
win0: 0x2，0x3
win1: 0x4，0x5
Cluster1:
win0: 0x6，0x7
win1: 0x8，0x9
Esmart0: 0xa, 0xb
Esmart1: 0xc, 0xd
Lut: 0xe[for vp0/2, will be used at different time]
AXI1:
Cluter2:
win0: 0x2，0x3
win1: 0x4，0x5
Cluster3:
win0: 0x6，0x7
win1: 0x8，0x9
Esmart2: 0xa，0xb
Esmart3: 0xc, 0xd
Lut: 0x1[for vp1]
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Iae865835e49ba8ca0197b0f015d7709cba23e8b3
Organize the code, separate rga_job_assign to rga_policy.c
Signed-off-by: Li Huang <putin.li@rock-chips.com>
Change-Id: Ie84cd14db23fba35db2da7c77edecb5b5bcc621b
addr_vir contains several pages, therefore must to
use free_pages instead of free_page to free memory.
Signed-off-by: Lin Jinhan <troy.lin@rock-chips.com>
Change-Id: Icb65f569674b31bb2a6c62f693a2968f24d709a6
This patch aims to configure pcie for better compatibility.
1.PLL LPF C1 85pf R1 1.25kohm
2.ck100m_pcie from PLL
Change-Id: I5115cf6ce7341c0891f13639f2c59db86ae9014b
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Support hdmi frl mode and dsc function.
Support max 8K-60Hz RGB 10bit output.
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Change-Id: Ibc2d48e2b25bc94e4be7ffa9703c400436bdee36
Don't need to direct callback via rk3308 jack detect, since
the sound component supports to set jack.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Change-Id: Ibdf86d06f69bd0a8885de753f632236b43b5800c
1. Disable interface clock at initial state.
2. Set the default tx dll tap value to 0xA for hs400.
3. Configure the parameters of enhanced strobe before enable HS400ES.
4. Set the default cmd dll tap value to 0x8.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I82f09c4d5f5f3b79f71b61fbe62eec6e8d6a7230
Because the CAP parameters of AHCI are incorrect, FBS cannot
be started automatically and needs to be configured manually.
This configuration can improve the read-write performance
when connecting multiple SATA hard disks through the PM chip.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I66ff92dce1711e3d189801c8caa3219217a50dda
The sata need pipe clock for the interface and asic clock
for the phy.
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Change-Id: I6069bd653a3f22da8ade0cab002c5346c9880cef
This patch adds a driver for the CellWise cw2017 fuel gauge.
Signed-off-by: Shunqing Chen <csq@rock-chips.com>
Change-Id: I29ae790727e0b2b326c46b452b7691f0231c6bfa
the wakeup interrupt handler which is guaranteed not to run while
@resume noirq() is being executed. the patch can help to avoid the
wakeup source try to access spi when the spi is in suspend mode.
Signed-off-by: shengfei Xu <xsf@rock-chips.com>
Change-Id: I3e6bc6e05dddeedea4c82de45a9e06b40e870876
The attachment and sg_table will be store in dma-buf-cache.
So use dma-buf-cache api instead of dma-buf api to reduce
the actual operation of attach/map.
Signed-off-by: Yandong Lin <yandong.lin@rock-chips.com>
Change-Id: I8b46c8f6a6f69ebe9854858e198d1c312a808a2f
Replace IOMMU_TLB_SHOT_ENTIRE by shootdown_entire defined in
iommu DT node for clean IOMMU framework code and more convenient
for masters. The master should call iommu_flush_iotlb_all to
zap cache manually.
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Herman Chen <herman.chen@rock-chips.com>
Change-Id: I5feab72fa12782d0715ad84a98cbd96a88bcd598
for vp2/vp3, we can use hardware or software TE to sync with panel ram,
but for vp1->dsc1->dsc1 path, we only can use software TE to sync with panel
ram.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
Change-Id: I0f54723c5c1c45916e669ce21819a127dc5b415d
