1.Add pinctrl config in rockchip_pwm_set_freq_meter().
2.Add input_sel flag to select the input of io or cru.
3.Use usleep_range() instead of readl_relaxed_poll_timeout,
because there is no need to poll interrupt status.
Change-Id: I6ea4456539fe143baf2bfce70386c51f801a00a3
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
1.Select pinctrl state in capture mode.
2.Use usleep_range() instead of readx_poll_timeout, because
there is no need to poll capture_cnt and the read
of capture_cnt may be interrupted.
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Change-Id: I9360a42aca374ed5eb089befd05571c4d32038f2
1.Add pinctrl config in rockchip_pwm_global_ctrl().
2.Config the dclk for grant channel in PWM_GLOBAL_CTRL_ENABLE
and PWM_GLOBAL_CTRL_DISABLE commands.
3.Add flag is_clk_enabled to confirm the status of dclk.
Change-Id: I9a377d6a72d2f242f9df5e707c42d86db0c13f69
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Using macro will be more efficient if related function
is called frequently.
In addition, remove unused parameter cntr in struct
rockchip_pwm_regs for pwm v1.
Change-Id: I7a1d5aa6e08845afc9501756dadacef09f527a13
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The RK3576 SoC has six channels TS-ADC(TOP, BIG_CORE, LITTLE_CORE
DDR, NPU and GPU).
Signed-off-by: Ye Zhang <ye.zhang@rock-chips.com>
Change-Id: I800dee18937d3d35243896fe22a953eac111ba3f
Add constants and callback functions for the dwmac on RK3576 soc.
As can be seen, the base structure is the same.
Change-Id: If5081998d98a20c6efe14992e00b719ae0ad0dd2
Signed-off-by: David Wu <david.wu@rock-chips.com>
These are ic debug reset, practically unusable.
Change-Id: Ibc5817ccf9d17abf35d1ff32c2a047866ef1dd2f
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
The RK3576 SoC has two independent USB2.0 PHYs, and
each PHY has one port.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I017dd09b83c8330c9f4a3d6d8a41eaa1d4c88df7
This adds the necessary data for handling otp on the rk3576.
Change-Id: I42536b05a24f32d0c98ceebe82aec5af9716513f
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
The pdm version 2 support more features:
1. Support gain control
2. Support more pdm clk, like 2.4Mhz
3. Support single channel single data
Signed-off-by: Jason Zhu <jason.zhu@rock-chips.com>
Change-Id: I3651e4416b30e84f0796a3a09574f39908adbfb5
Rockchip platform will put phase settings into dw_mmc controller
instead. For USRID register, 0x20230002 stands for that this new
feature is implemented.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ida9d25f7631fe57b87c70832671973bb97d9f82f
In DPTX Controller, when hpd signal is low, the hpd state will
change to unplug immediately. if the low level signal is less
than 2ms, the hpd state will change to plug state and trigger a
hpd irq interrupt.
In some case, driver will detect hpd state to get the plug/unplug
info when a hpd irq is coming. A hpd irq may be regard as a unplug
state. To avoid this issue, it better to wait the hpd state change
to the nest state.
Change-Id: I68c5bdc72128a2bc3ea990cfcb54e2ade755abc7
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
For RK3576 YUV420 output, hden signal introduce one cycle delay,
so we need to adjust hfp and hbp to compatible with this design.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I272f3e145bfe216b1d76f6313c43180040590deb
Some platform VP can't support BCSH, add some log to remind this info
when userspace want to enable BCSH at unsupported VP.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I8247475edad30e14f08ef8c23e8314916c57a1f4
when enable dp, it need config as follow:
1. enable dp link clk;
2. config dp regs;
3. enable dp video stream;
4. enable vop data stream.
when disable dp, it need config as follow:
1. disable vop data steam.
2. disable dp video stream;
3. disable dp link clk.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Icd5407da090f137e02d3028b01576ea157401a8a
pre_scan_hblank minimum value is 8, otherwise the win reset signal
lead to first line data be zero.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ibef722cd65a9f7e276ba1ffda1d75cac2ac8b83a
At writeback oneshot mode, the writeback auto gating will close clk after
VOP writeback complete, but at this time, the writeback axi access maybe
uncomplete, this will lead to writeback state error and iommu stall failed.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I4a74a8ace1cf6dba6d60af822e0d74d31d7f61fa
Different hdmi sinks have different compatibility issues.
Many of the solutions are conflicting between different sinks,
So special treatment is needed for different sinks.
Only VSI-related quirks are currently supported, new functions
are gradually supported.
Change-Id: I3aaf654424502380d460b3e9d2229a4cdc56dcb1
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
If less this commit, Cluster will be display black and appear
POST_BUF_EMPTY.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ia0505bdb3917624725bb288e089fb88abbe9972e
win axi id register is 5 bits, but lut/dci axi id is 4 bits, so lut axi id
should be less then 0xf;
Cluster0 win0: 0x10, 0x11 [AXI0]
Cluster0 win1: 0x12, 0x13 [AXI0]
Cluster1 win0: 6, 7 [AXI0]
Cluster1 win1: 8, 9 [AXI0]
Esmart0: a, b [AXI0]
Esmart1: c, d [AXI0]
Esmart2: a, b [AXI1]
Esmart3: c, d [AXI1]
Lut dma rid: 0x1, 0x2, 0x3 [AXI0]
DCI dma rid: 0x4 [AXI0]
Metadata rid: 0x5 [AXI0]
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: If1148aba4ab5242470511b356ee53db9cccef1eb
If hdmi ddc sda and scl fall edge phase difference
is too small, support configure the sda falling edge
in dts.
The delay range is 0-76800 ns.
Change-Id: I116137d8e6b9adac1262a8e658320845281555b5
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
1.set dsi lane to LP11 status before powering on the sceen
2.Support for init codes can be transmitted at LP or HS mode
3.HS clk comes out when the high-speed video signal is sent
Change-Id: I192a9b9d6ac3fb0cdbb4b4d462203e97c6427028
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
If less this commit, esmart port sel will be set error val and lead to
esmart register can't take effect, this will lead to like iommu
pagefault issues.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: If2c80a683b81d1ad00bdea9f2c09da90a5f55964
1.Fix the shift of reg grf_mipi_1to4_en to 0.
2.Set grf_mipi_mode to 0(video mode) if using display path
vopl->1to4->mipi.
3.Add configuration of reg out_dresetn, which should be
set to 1 if using display path vopl->1to4->edp/hdmi/mipi.
4.Set reg grf_hdmi_1to4_en to 1 if using display path
vopl->1to4->hdmi.
Change-Id: Ia19725f69382d6b0d2a710c17b9ac1c8a284ddf5
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The RGB888 bus_format can be converted to VYU444 if r2y
enabled, so it is needed to enable rb_swap and rg_swap
for YUV444.
Change-Id: Ib35398137dcd3c849590ba5243d879c5ef11ccee
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Set timer reference base According to the actual
refclk frequency, otherwise cec or ddc function
may be abnormal.
Change-Id: Id45af649182a5158a47ee2cadb1254f2dc855d52
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
