For RK3576 YUV420 output, hden signal introduce one cycle delay,
so we need to adjust hfp and hbp to compatible with this design.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I272f3e145bfe216b1d76f6313c43180040590deb
Some platform VP can't support BCSH, add some log to remind this info
when userspace want to enable BCSH at unsupported VP.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I8247475edad30e14f08ef8c23e8314916c57a1f4
when enable dp, it need config as follow:
1. enable dp link clk;
2. config dp regs;
3. enable dp video stream;
4. enable vop data stream.
when disable dp, it need config as follow:
1. disable vop data steam.
2. disable dp video stream;
3. disable dp link clk.
Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
Change-Id: Icd5407da090f137e02d3028b01576ea157401a8a
pre_scan_hblank minimum value is 8, otherwise the win reset signal
lead to first line data be zero.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ibef722cd65a9f7e276ba1ffda1d75cac2ac8b83a
At writeback oneshot mode, the writeback auto gating will close clk after
VOP writeback complete, but at this time, the writeback axi access maybe
uncomplete, this will lead to writeback state error and iommu stall failed.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I4a74a8ace1cf6dba6d60af822e0d74d31d7f61fa
Different hdmi sinks have different compatibility issues.
Many of the solutions are conflicting between different sinks,
So special treatment is needed for different sinks.
Only VSI-related quirks are currently supported, new functions
are gradually supported.
Change-Id: I3aaf654424502380d460b3e9d2229a4cdc56dcb1
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
If less this commit, Cluster will be display black and appear
POST_BUF_EMPTY.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: Ia0505bdb3917624725bb288e089fb88abbe9972e
win axi id register is 5 bits, but lut/dci axi id is 4 bits, so lut axi id
should be less then 0xf;
Cluster0 win0: 0x10, 0x11 [AXI0]
Cluster0 win1: 0x12, 0x13 [AXI0]
Cluster1 win0: 6, 7 [AXI0]
Cluster1 win1: 8, 9 [AXI0]
Esmart0: a, b [AXI0]
Esmart1: c, d [AXI0]
Esmart2: a, b [AXI1]
Esmart3: c, d [AXI1]
Lut dma rid: 0x1, 0x2, 0x3 [AXI0]
DCI dma rid: 0x4 [AXI0]
Metadata rid: 0x5 [AXI0]
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: If1148aba4ab5242470511b356ee53db9cccef1eb
If hdmi ddc sda and scl fall edge phase difference
is too small, support configure the sda falling edge
in dts.
The delay range is 0-76800 ns.
Change-Id: I116137d8e6b9adac1262a8e658320845281555b5
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
1.set dsi lane to LP11 status before powering on the sceen
2.Support for init codes can be transmitted at LP or HS mode
3.HS clk comes out when the high-speed video signal is sent
Change-Id: I192a9b9d6ac3fb0cdbb4b4d462203e97c6427028
Signed-off-by: Guochun Huang <hero.huang@rock-chips.com>
If less this commit, esmart port sel will be set error val and lead to
esmart register can't take effect, this will lead to like iommu
pagefault issues.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: If2c80a683b81d1ad00bdea9f2c09da90a5f55964
1.Fix the shift of reg grf_mipi_1to4_en to 0.
2.Set grf_mipi_mode to 0(video mode) if using display path
vopl->1to4->mipi.
3.Add configuration of reg out_dresetn, which should be
set to 1 if using display path vopl->1to4->edp/hdmi/mipi.
4.Set reg grf_hdmi_1to4_en to 1 if using display path
vopl->1to4->hdmi.
Change-Id: Ia19725f69382d6b0d2a710c17b9ac1c8a284ddf5
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
The RGB888 bus_format can be converted to VYU444 if r2y
enabled, so it is needed to enable rb_swap and rg_swap
for YUV444.
Change-Id: Ib35398137dcd3c849590ba5243d879c5ef11ccee
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
Set timer reference base According to the actual
refclk frequency, otherwise cec or ddc function
may be abnormal.
Change-Id: Id45af649182a5158a47ee2cadb1254f2dc855d52
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
Reg mem_clk_auto_gating can help to gate the clock for
accessing HDCP memory automatically.
Change-Id: I04188d59e4273cfb61551cd01ca53f336d2bf1aa
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
For rk3576, vopl supports eDP/HDMI/MIPI by the 1to4
module, which can transfer 1 pixle/cycle data from
vopl to 4 pixle/cycle data for HDMI/MIPI controllers.
Change-Id: I0da688d53c92a93e55778da2cce17596a22f540e
Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
SHARP mainly completes the enhancement of image
details, which can support the configuration of
different intensity gains for different scales
and different directions of details.
Only vp0 support SHARP and rgb input is not
supported. SHARP shares line buffer with
post scaler, so the two functions are mutually
exclusive.
Change-Id: Id4887594821640d6685a76a7094bbb57c6d50b21
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
DCI mainly completes the dynamic adjustment of the
brightness and contrast of the picture according to
the brightness distribution of the current picture,
so that the picture appears more transparent.
Only cluster0 supports DCI, suitable for minimum
resolution of 128 x 128 and maximum resolution of
4096 x 2160.
Change-Id: I1836d2d317172859b7df971ce4f4fb5dfb1b4c83
Signed-off-by: Algea Cao <algea.cao@rock-chips.com>
RK3576 VOP have 2 Cluster win and 4 Esmart win, this win be used
by 3 video ports as following roles:
* VP0 can use Cluster0/1 and Esmart0/2
* VP1 can use Cluster0/1 and Esmart1/3
* VP2 can use Esmart0/1/2/3
In additions, RK3576 VOP can support DCI/ACM/CSC/HDR/SHARP/GAMMA/3D LUT/POST SCALE/BCSH
etc. post process.
Signed-off-by: Sandy Huang <hjc@rock-chips.com>
Change-Id: I89f656e847f758f9d3d57ee0c137b29196de6737
This driver is modified to support RK3576 SoCs.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Id933108d90a2850b82779a7328563a3b0812e703
According to a description from TRM, add all the power domains.
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: Ia9361658401641acbaec8b4853a07507dcf48404
Add the clock tree definition for the new RK3576 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Change-Id: I85c05295394032485f146efbaf8aee9044685bfa
Add the dt-bindings header for the rk3576, that gets shared between
the clock controller and the clock references in the dts.
Add softreset ID for rk3576.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: I6aff7360d4ff95266134394e66e0987c59906905
Document the device tree bindings of the rockchip Rk3576 SoC
clock driver in
Documentation/devicetree/bindings/clock/rockchip,rk3576-cru.yaml.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I4f80de8accd78e29a3bac0a8ef9c2c9ef946bb94
For soc has less 15 UARTS, bur more than 10, like rk3576
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: I3bfdfa7414a080864e8d154dec8e1691c21a9ab0
