+CONFIG_WL_ROCKCHIP=y
+CONFIG_WIFI_BUILD_MODULE=y
+CONFIG_AP6XXX=m
+CONFIG_BCMDHD_PCIE=y
-# CONFIG_NET_VENDOR_REALTEK is not set
+CONFIG_R8168=y
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Change-Id: Icb986d4e419054beb5bb271f37f965e9120348ce
1. set hp-det pin pcfg_pull_none all evbs
2. enable headset for rk3588s-tablets
3. add "everest,es8323" string to es8388 compatible property for rk3588s-tablets
Signed-off-by: Shunhua Lan <lsh@rock-chips.com>
Change-Id: I85ae0bc78c2058d38ed768da7233d86cdb0c301f
In order to adapt to the mpu6500 in the rk3588
evb3 board, a new layout was added.
Change-Id: I9283e05e7b8b3ec04ee887e36898c4c49e4efa51
Signed-off-by: Wang Jie <dave.wang@rock-chips.com>
If the port is going to send Discover_Identity Message, vdm_sm_running
flag was intentionally set before entering Ready States in order to
avoid the conflict because the port and the port partner might start
AMS at almost the same time after entering Ready States.
However, the original design has a problem. When the port is doing
DR_SWAP from Device to Host, it raises the flag. Later in the
tcpm_send_discover_work, the flag blocks the procedure of sending the
Discover_Identity and it might never be cleared until disconnection.
Since there exists another flag send_discover representing that the port
is going to send Discover_Identity or not, it is enough to use that flag
to prevent the conflict. Also change the timing of the set/clear of
vdm_sm_running to indicate whether the VDM SM is actually running or
not.
Change-Id: Id282f7b694cb608a5632db43dafd82dade77340f
Fixes: c34e85fa69 ("usb: typec: tcpm: Send DISCOVER_IDENTITY from dedicated work")
Cc: stable <stable@vger.kernel.org>
Cc: Badhri Jagan Sridharan <badhri@google.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Kyle Tso <kyletso@google.com>
Link: https://lore.kernel.org/r/20210826124201.1562502-1-kyletso@google.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit ef52b4a9fc)
Commit a20dcf53ea ("usb: typec: tcpm: Respond Not_Supported if no
snk_vdo"), stops tcpm_pd_data_request() calling tcpm_handle_vdm_request()
when port->nr_snk_vdo is not set. But the VDM might be intended for an
altmode-driver, in which case nr_snk_vdo does not matter.
This change breaks the forwarding of connector hotplug (HPD) events
for displayport altmode on devices which don't set nr_snk_vdo.
tcpm_pd_data_request() is the only caller of tcpm_handle_vdm_request(),
so we can move the nr_snk_vdo check to inside it, at which point we
have already looked up the altmode device so we can check for this too.
Doing this check here also ensures that vdm_state gets set to
VDM_STATE_DONE if it was VDM_STATE_BUSY, even if we end up with
responding with PD_MSG_CTRL_NOT_SUPP later.
Note that tcpm_handle_vdm_request() was already sending
PD_MSG_CTRL_NOT_SUPP in some circumstances, after moving the nr_snk_vdo
check the same error-path is now taken when that check fails. So that
we have only one error-path for this and not two. Replace the
tcpm_queue_message(PD_MSG_CTRL_NOT_SUPP) used by the existing error-path
with the more robust tcpm_pd_handle_msg() from the (now removed) second
error-path.
Change-Id: I5ccff5715cf08e2f8ba825eae4fc7cbdf43f1970
Fixes: a20dcf53ea ("usb: typec: tcpm: Respond Not_Supported if no snk_vdo")
Cc: stable <stable@vger.kernel.org>
Cc: Kyle Tso <kyletso@google.com>
Acked-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Acked-by: Kyle Tso <kyletso@google.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Link: https://lore.kernel.org/r/20210816154632.381968-1-hdegoede@redhat.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
(cherry picked from commit 5571ea3117)
pcie30phy will need to reference to pipe-grf.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I31e55c33c22fa4a2bcf424ad4730e057a6fbca28
rk3588 pcie3 phy has a pcie3_phymode to decide how to use the four
lanes, add support in dts so that we can customize in dts.
The phy has two port and each port has two lane:
pcie30_phy_mode[2:0]
2: aggregation
1: bifurcation for port 1
0: bifurcation for port 0
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I0546329cc53df05f0779a7b34d948158bbc5ebcd
Add support for RK3588 PCIe3.0 phy, and make it more
flexible for later platforms.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Change-Id: Ied29cfcdf69d84ab2a6d653259170b9d2c484a06
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
The utmi clk is provided by the USB PHY for the USB controller.
And the utmi clk is disabled if the USB PHY enter suspend mode.
The current charge detection sets the USB PHY in suspend mode
at first, then take about hundreds of milliseconds to do charge
detection, in other words, the utmi clk will be disabled hundreds
of milliseconds. It may cause the USB controller work abnormally
during the charge detection.
Actually, the conditions for charger detection is:
1. Set the utmi_opmode in non-driving mode.
2. Set the utmi_xcvrselect to FS speed.
3. Set the utmi_termselect to FS speed.
4. Enable the DP/DM pulldown resistor.
This patch adds a new chg_mode to set the PHY in charge detection
mode according to the above conditions, and set the PHY in normal
mode to keep the utmi clk at the same time.
Signed-off-by: William Wu <william.wu@rock-chips.com>
Change-Id: I1cbf565d5145bdae5bc91132bc5fbff23a5cc443
DSC registers can only be accessed after DSC_PD
power on.
We don't want to power on PD at vop_initial.
We will enable PD when a corresponding module
is enabled.
And enable all PD at vop_inital make it more
complicated for the nest pd(PD_CLUSTER0/1/2/3)
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I362ace6837b24a0ebed5b8486c4ba46680d0e693
HDMI on rk3588 have a inverted V/HSYNC polarity than
other platform.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I84fc369c211a6f8715c77421c0938fe05516fca6
This is the Linux device driver released for RealTek RTL8168B/8111B,
RTL8168C/8111C, RTL8168CP/8111CP, RTL8168D/8111D, RTL8168DP/8111DP,
and RTL8168E/8111E Gigabit Ethernet controllers with PCI-Express interface.
Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Change-Id: I54634ade9602706d1230bb2551f1da7157943814
1.version: 101.10.361.11 (wlan=r892223-20210630-1)
2.both wifi5 and wifi6 are supported
Signed-off-by: Alex Zhao <zzc@rock-chips.com>
Change-Id: Ia0724ebc628ba40afed947275d34ff5c47a410b4
of_iomap allowed to map the same address repeatedly.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Change-Id: I670e2f3ed564c159eed825bc388f4a9ae3a65f76
Reorder system heap pages by bit[14:12] of pages' physical address, it
benefit for dram do access in different banks once time.
Signed-off-by: Simon Xue <xxm@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Change-Id: I686c9e54f456d3b7f373ab1b0586125e70f891ec
Two axi bus:
AXI0 is a read/write bus with a higher performance.
AXI1 is a read only bus.
Every window on a AXI bus must assigned two unique
read id(yrgb_id/uv_id, valid id are 0x1~0xe).
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Change-Id: I867df219797da33f89fec6fba639bcdf55cb54b3
Support the system_heap to allow cpu access partial dma-buf.
Change-Id: I8250c0bb26b776b8c8f5e4c3ee0cb71e26445743
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Add DMA_BUF_IOCTL_SYNC_PARTIAL support for user to sync dma-buf with
offset and len.
Change-Id: I03d2d2e10e48d32aa83c31abade57e0931e1be49
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Bt command think if EL0_SP is less than 0xffffffcxxxxxxxxx
it is user mode, but EL0_SP may be 0xffffff8xxxxxxxxx.
According to ARM-V8, the virtual address bit63 determine
TTBR0 OR TTBR1. So if EL0_SP is less than 0x8000000000000000,
it is user mode.
Signed-off-by: Huibin Hong <huibin.hong@rock-chips.com>
Change-Id: Ib97b405df6e669e3806161c97801847e2f5d247a
The controller must route to the comboPHY when it works.
pcie1l0_sel
Select the signal form PHY to PCIe1l0
1'b0: Select comb PHY
1'b1: Select PCIE3 PHY
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I5e7faf71fdd22958c757f884f75ec9a00aeb2fb9
Add dts decode to support the pcie2x1l0 and pcie2x1l1 setting, which is
in PHP_GRF_PCIESEL_CON.
pcie1l0_sel
Select the signal form PHY to PCIe1l0
1'b0: Select comb PHY
1'b1: Select PCIE3 PHY
Usage in dts:
rockchip,pcie1ln-sel-bits = <0x100 0 0 0>;
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Change-Id: I5fb177f37b23c5f3cdaadf8c103f8e6487ea6a76
Currently, the datasheet and pcb design has removed all the
pin {bclk, lrck}_rx, and use the pin {bclk, lrck}_tx only
to simpilify design.
- Remove pin {bclk, lrck}_rx
- Rename pin {bclk, lrck}_tx to [bclk, lrck]
So, we do the same thing by default.
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Change-Id: Ide90500b766fa39d6f032b0edf309e001939b579
