to fix up :
[ 0.000000] clk: couldn't get clock 4 for /clock-controller@ff760000
[ 0.000000] rockchip_clk_of_add_provider: could not register clk provider
The cause of the error:
struct clk *__clk_create_clk(struct clk_hw *hw, const char *dev_id,
const char *con_id, bool with_orphans)
{
/* This is to allow this function to be chained to others */
if (!hw || IS_ERR(hw))
return (struct clk *) hw;
if (hw->core->orphan && !with_orphans)
return ERR_PTR(-EPROBE_DEFER);
return clk_hw_create_clk(hw, dev_id, con_id);
}
if clk is orphan and not have the with_orphans flag, it will
register clk provider failed.
Change-Id: I87ca9ec087611a5425545bfc857b09d8438218b5
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This patch adds "snps,xhci-trb-ent-quirk" for DWC3 controllers
in RK1808/RK3328/RK3399/RK3399pro-npu.
Change-Id: I708f62747150316d66459f02b399d7c9b2667636
Signed-off-by: William Wu <william.wu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
It has been reported that xHCI on this SoC really cannot
sleep without extraordinary delay. This quirk can ensure
the xHCI enter the Halted state after the Run/Stop (R/S)
bit is cleared to '0'.
Change-Id: Ibccf0c5c2da4533817b998b523e3a3a09ed7dcea
Signed-off-by: Wu Liang feng <wulf@rock-chips.com>
rk previous SOCs such as rk3126 have no tsadc module, so a virtual tsadc is
implemented to control the thermal problem.
the virtual tsadc is designed on considering 2 factors, one is heating
modules' heating time and the working frequences, the other one is current
leval monitored by coulometer.
Change-Id: I0c7d8b952004d4f7918a41c925c50d38aaa65673
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Due to 32k clock jitter, tsadc will wrongly report a very
high temperature, that is a temperature-jump. This may lead
to an abnormal OS reboot. A filter function is added to
predict the true temperature.
Change-Id: I5b5641efe8e64b4058a604f274350b1e94584fa6
Signed-off-by: Rocky Hao <rocky.hao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
In order not to affect other clocks, remove the apll from the
parent list of other clocks and only core, mac and lcdc can
select apll as parent.
Change-Id: I58b995f8ccf69c6564f74b5823f618a186030d70
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Some clocks may get disabled as a side effect of another clock
being disabled, because have no consumers. Says the dclk_hdmi's parent may
change from apll to gpll, but the apll's son clocks are very less.
Change-Id: I4fb4e5fdf83a8f73979b50dbcf4f3e4543896fcf
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
1. The first parent name of sclk_cif_out_src is wrong, it is
"sclk_cif_src".
2. The MUX configuration for sclk_cif_out_src is wrong, it should
be muxdiv_offset=29, mux_shift=2, mux_width=1.
Change-Id: I36a0ec0791afdef398d37ac8b92b7831619fb01b
Signed-off-by: Liang Chen <cl@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
The clock hevc core will be used to drive the hevc decoder.
Change-Id: Ic1298ce1edd07f86e5c243e3a2c9876481f4cba9
Signed-off-by: Randy Li <randy.li@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
npll is just for dclk_vop, others clk not allowed to set npll as parent.
Change-Id: I11e1770acab5486acaebafd56a0c57847f7f533c
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This flag was in place to prevent important clocks from getting gated
while they had no users. Now that the driver supports clocks
properly, we can drop this.
Change-Id: I91d0a5c000ed7215bf55dbc871e175ac79a1cd2a
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
If frac clk parent rate is PLL rate, but still lower
than frac rate*20, not allowed fractional div.
Change-Id: I09c93e1d8f32c0a4e345057964d58505b1477204
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
This flag was in place to prevent important clocks from getting gated
while they had no users. Now that the DSI driver supports clocks
properly, we can drop this.
Change-Id: Ibdc1210d5ec97ec53dfff9bd989b2297b070ff28
Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
with the NB parameter,can adjust the jitter of the output PLL.
make the npll jitter is better,make it more suitable for DCLK display.
Change-Id: I9d819bdc2b520205a7d63ee8ed83643601ccc821
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Some PLL_NUX_CLKs' gates is actually behind muxs according to latest TRM,
so move the gates to composite clocks and amend their parent clocks.
Change-Id: Ib6043caa61e9df0473f2d0bdc756850968bb2a55
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Fix a typo making the aclk_gpu and aclk_gpu_noc access a wrong register to
handle its gate.
Change-Id: Ie0bac8014363af7c0409b8a56eacf2e858818843
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
set rtc stopped by default, start rtc in rtc device probe.
add rtc node, whether RTC need to initialize.
Change-Id: Ifab269786f316d33149a50a18e23af1b6206d57d
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add a ddrc clock into clk branches, so we can do ddr frequency
scaling on rk3288 platform in future.
Change-Id: Ia6c93e5ce82fa30475eddf051bc9ea2512b0cc07
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Cat ddr frequency from rockchip_ddrclk_scpi_set_rate prior to
rockchip_ddrclk_scpi_recalc_rate, to optimizing running time and reduce
SCPI APIs usage rate.
Change-Id: Iba31d33a5920816b1cc230f639ea3a9503d451c8
Signed-off-by: Tang Yun ping <typ@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Add a ddrc clock into clk branches, so we can do ddr frequency
scaling on rk3368 platform in future.
Change-Id: Ie7fd2e8d8bdf8b9ff843ca13e848f772adaa109a
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
On rk3368, let a mcu scaling ddr clock via SCPI (System Control and
Power Interface) APIs.
Change-Id: I95342b876caad991e6d1319c5e4ec793365c7981
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
CPLL and NPLL is used for vop dclk, sync rate flag would cause
loader display abnormal.
Change-Id: Ia170a8d0b7d1f39e2c9dcbc10b5d33fd1886d5f7
Signed-off-by: Mark Yao <mark.yao@rock-chips.com>
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Reference the newly added efuse clock-ids in the clock-tree.
Change-Id: Ibbef52bcc44d006ab48e6f1f874e3bc88c681bd6
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
